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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

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This commit is contained in:
Blaise Tine
2020-12-19 02:45:06 -08:00
parent 29cd2f5dff
commit 4bbd7bf408
76 changed files with 1313 additions and 1098 deletions
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17
hw/rtl/VX_csr_arb.v
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@@ -43,8 +43,19 @@ module VX_csr_arb (
assign csr_io_req_if.ready = csr_pipe_req_if.ready && !csr_core_req_if.valid;
// responses
assign csr_io_rsp_if.valid = csr_pipe_rsp_if.valid & select_io_rsp;
assign csr_io_rsp_if.data = csr_pipe_rsp_if.data[0];
wire csr_io_rsp_ready;
VX_skid_buffer #(
.DATAW (32)
) csr_io_out_buffer (
.clk (clk),
.reset (reset),
.valid_in (csr_pipe_rsp_if.valid & select_io_rsp),
.data_in (csr_pipe_rsp_if.data[0]),
.ready_in (csr_io_rsp_ready),
.valid_out (csr_io_rsp_if.valid),
.data_out (csr_io_rsp_if.data),
.ready_out (csr_io_rsp_if.ready)
);
assign csr_commit_if.valid = csr_pipe_rsp_if.valid & ~select_io_rsp;
assign csr_commit_if.wid = csr_pipe_rsp_if.wid;
@@ -54,6 +65,6 @@ module VX_csr_arb (
assign csr_commit_if.wb = csr_pipe_rsp_if.wb;
assign csr_commit_if.data = csr_pipe_rsp_if.data;
assign csr_pipe_rsp_if.ready = select_io_rsp ? csr_io_rsp_if.ready : csr_commit_if.ready;
assign csr_pipe_rsp_if.ready = select_io_rsp ? csr_io_rsp_ready : csr_commit_if.ready;
endmodule