performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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@@ -66,7 +66,7 @@ make ase
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./run_ase.sh build_ase_1c ../../benchmarks/opencl/vecadd/vecadd
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# modify "vsim_run.tcl" to dump VCD trace
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vcd file vortex.vcd
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vcd file trace.vcd
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vcd add -r /*/Vortex/hw/rtl/*
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run -all
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@@ -104,8 +104,11 @@ lsof +D build_ase_1c
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make -C pipeline clean && make -C pipeline > pipeline/build.log 2>&1 &
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make -C cache clean && make -C cache > cache/build.log 2>&1 &
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make -C core clean && make -C core > core/build.log 2>&1 &
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make -C core8 clean && make -C core8 > core8/build.log 2>&1 &
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make -C vortex clean && make -C vortex > vortex/build.log 2>&1 &
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make -C top clean && make -C top > top/build.log 2>&1 &
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make -C top1 clean && make -C top1 > top1/build.log 2>&1 &
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make -C top8 clean && make -C top8 > top8/build.log 2>&1 &
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# How to calculate the maximum operating frequency?
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200 Mhz -> period = 1/200x10^6 = 5ns
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@@ -1,6 +1,6 @@
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#!/bin/bash
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SCRIPT_DIR=$PWD
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SCRIPT_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
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BUILD_DIR=$1
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@@ -4,21 +4,21 @@
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+define+QUARTUS
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+define+FPU_FAST
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#+define+SCOPE
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+define+PERF_ENABLE
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#+define+PERF_ENABLE
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+define+DBG_PRINT_CORE_ICACHE
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+define+DBG_PRINT_CORE_DCACHE
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+define+DBG_PRINT_CACHE_BANK
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+define+DBG_PRINT_CACHE_SNP
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+define+DBG_PRINT_CACHE_MSRQ
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+define+DBG_PRINT_CACHE_TAG
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+define+DBG_PRINT_CACHE_DATA
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+define+DBG_PRINT_DRAM
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+define+DBG_PRINT_PIPELINE
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+define+DBG_PRINT_OPAE
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+define+DBG_PRINT_AVS
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+define+DBG_PRINT_SCOPE
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+define+DBG_CACHE_REQ_INFO
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#+define+DBG_PRINT_CORE_ICACHE
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#+define+DBG_PRINT_CORE_DCACHE
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#+define+DBG_PRINT_CACHE_BANK
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#+define+DBG_PRINT_CACHE_SNP
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#+define+DBG_PRINT_CACHE_MSRQ
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#+define+DBG_PRINT_CACHE_TAG
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#+define+DBG_PRINT_CACHE_DATA
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#+define+DBG_PRINT_DRAM
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#+define+DBG_PRINT_PIPELINE
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#+define+DBG_PRINT_OPAE
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#+define+DBG_PRINT_AVS
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#+define+DBG_PRINT_SCOPE
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#+define+DBG_CACHE_REQ_INFO
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vortex_afu.json
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QI:vortex_afu.qsf
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@@ -1,5 +1,5 @@
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+define+NUM_CORES=2
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+define+L2_ENABLE=0
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+define+SYNTHESIS
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+define+QUARTUS
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+define+FPU_FAST
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@@ -1,5 +1,5 @@
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+define+NUM_CORES=4
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+define+L2_ENABLE=1
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+define+SYNTHESIS
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+define+QUARTUS
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+define+FPU_FAST
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@@ -1,5 +1,7 @@
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# Analysis & Synthesis Assignments
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
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set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
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set_global_assignment -name VERILOG_MACRO QUARTUS
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@@ -7,7 +9,14 @@ set_global_assignment -name VERILOG_MACRO SYNTHESIS
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set_global_assignment -name VERILOG_MACRO NDEBUG
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set_global_assignment -name MESSAGE_DISABLE 16818
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set_global_assignment -name VERILOG_MACRO FPU_FAST
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set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
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set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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@@ -17,10 +26,4 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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set_global_assignment -name POWER_USE_TA_VALUE 65
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set_global_assignment -name SEED 1
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
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set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
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set_global_assignment -name SEED 1
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