performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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@@ -9,7 +9,7 @@
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#define CCI_WQ_SIZE 16
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#define ENABLE_DRAM_STALLS
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#define DRAM_LATENCY 100
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#define DRAM_LATENCY 24
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#define DRAM_RQ_SIZE 16
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#define DRAM_STALLS_MODULO 16
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