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allowing partial cache request submissions, io bus support broken

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This commit is contained in:
Blaise Tine
2020-12-21 03:53:13 -08:00
parent 4bbd7bf408
commit 4b7d871d62
24 changed files with 342 additions and 968 deletions
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56
hw/rtl/fp_cores/altera/acl_gen.log
View File

@@ -5,15 +5,15 @@ Generation context:
HardFP is enabled enabling set to true
Faithful rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_fdiv
The new component name is acl_s10_fdiv
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 539, DSPs 5, RAMBits 32768, RAMBlocks 3
The pipeline depth of the block is 15 cycle(s)
Deployment FPGA Stratix10
Estimated resources LUTs 681, DSPs 5, RAMBits 32768, RAMBlocks 3
The pipeline depth of the block is 25 cycle(s)
@@start
@name FPDiv@
@latency 15@
@LUT 539@
@latency 25@
@LUT 681@
@DSP 5@
@RAMBits 32768@
@RAMBlockUsage 3@
@@ -34,15 +34,15 @@ Generation context:
HardFP is enabled enabling set to true
Faithful rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_fsqrt
The new component name is acl_s10_fsqrt
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 271, DSPs 3, RAMBits 15872, RAMBlocks 3
The pipeline depth of the block is 10 cycle(s)
Deployment FPGA Stratix10
Estimated resources LUTs 349, DSPs 3, RAMBits 15872, RAMBlocks 3
The pipeline depth of the block is 17 cycle(s)
@@start
@name FPSqrt@
@latency 10@
@LUT 271@
@latency 17@
@LUT 349@
@DSP 3@
@RAMBits 15872@
@RAMBlockUsage 3@
@@ -62,15 +62,15 @@ Generation context:
HardFP is enabled enabling set to true
Faithful rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_ftoi
The new component name is acl_s10_ftoi
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 327, DSPs 0, RAMBits 0, RAMBlocks 0
Deployment FPGA Stratix10
Estimated resources LUTs 344, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPToFXP@
@latency 3@
@LUT 327@
@LUT 344@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@@ -90,15 +90,15 @@ Generation context:
HardFP is enabled enabling set to true
Faithful rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_ftou
The new component name is acl_s10_ftou
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 287, DSPs 0, RAMBits 0, RAMBlocks 0
Deployment FPGA Stratix10
Estimated resources LUTs 272, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 3 cycle(s)
@@start
@name FPToFXP@
@latency 3@
@LUT 287@
@LUT 272@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@@ -118,15 +118,15 @@ Generation context:
HardFP is enabled enabling set to true
Faithful rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_itof
The new component name is acl_s10_itof
Frequency 250MHz
Deployment FPGA Arria10
Estimated resources LUTs 397, DSPs 0, RAMBits 0, RAMBlocks 0
Deployment FPGA Stratix10
Estimated resources LUTs 362, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 7 cycle(s)
@@start
@name FXPToFP@
@latency 7@
@LUT 397@
@LUT 362@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@
@@ -146,15 +146,15 @@ Generation context:
HardFP is enabled enabling set to true
Faithful rounding constraint detected
Will not generate valid and channel signals
The new component name is acl_utof
The new component name is acl_s10_utof
Frequency 300MHz
Deployment FPGA Arria10
Estimated resources LUTs 363, DSPs 0, RAMBits 0, RAMBlocks 0
Deployment FPGA Stratix10
Estimated resources LUTs 310, DSPs 0, RAMBits 0, RAMBlocks 0
The pipeline depth of the block is 7 cycle(s)
@@start
@name FXPToFP@
@latency 7@
@LUT 363@
@LUT 310@
@DSP 0@
@RAMBits 0@
@RAMBlockUsage 0@

14
hw/rtl/fp_cores/altera/acl_gen.sh
View File

@@ -2,7 +2,7 @@
CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
OPTIONS="-target Arria10 -lang verilog -enableHardFP 1 -printMachineReadable -faithfulRounding -noChanValid -enable -speedgrade 2"
OPTIONS="-target Stratix10 -lang verilog -enableHardFP 1 -printMachineReadable -faithfulRounding -noChanValid -enable -speedgrade 2"
export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH
@@ -14,12 +14,12 @@ FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
echo Generating IP cores for $FBITS
{
$CMD -name acl_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0
$CMD -name acl_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS
$CMD -name acl_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
$CMD -name acl_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
$CMD -name acl_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
$CMD -name acl_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
$CMD -name acl_s10_fdiv -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0
$CMD -name acl_s10_fsqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS
$CMD -name acl_s10_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
$CMD -name acl_s10_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
$CMD -name acl_s10_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
$CMD -name acl_s10_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
} > acl_gen.log 2>&1
#cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv .