Using verilog For-loops + Passing all tests

2019-03-30 22:55:13 -04:00
parent 52a839f84d
commit 4aac33b298
11 changed files with 1622 additions and 439 deletions
--- a/rtl/VX_fetch.v
+++ b/rtl/VX_fetch.v
@@ -52,7 +52,6 @@ module VX_fetch (
 			for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
 				valid[ini_cur_th]   = 0; // Thread 1 active
 			valid[0]   = 1;
-			// valid[1]   = 0;
 			stall_reg  = 0;
 			delay_reg  = 0;
 			old        = 0;