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Simulate debug

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This commit is contained in:
felsabbagh3
2019-10-29 14:28:20 -04:00
parent 557c987bb0
commit 4aa04e76e6
12 changed files with 242 additions and 33 deletions
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9
rtl/modelsim/Makefile
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@@ -73,13 +73,20 @@ SRC = \
../shared_memory/VX_bank_valids.v \
../shared_memory/VX_priority_encoder_sm.v \
../shared_memory/VX_shared_memory.v \
../shared_memory/VX_shared_memory_block.v
../shared_memory/VX_shared_memory_block.v \
../../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \
../../models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v
# ../../models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
# vortex_dpi.h
CMD= \
-do "vcd file vortex.vcd; \
vcd add -r /vortex_tb/*; \
vcd add -r /vortex/*; \
run -all; \
quit -f"

2
rtl/modelsim/vortex_tb.v
View File

@@ -102,7 +102,7 @@ module vortex_tb (
if (out_ebreak) begin
gracefulExit();
$finish;
#20 $finish;
end
end