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minor update

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This commit is contained in:
Blaise Tine
2021-10-11 18:32:17 -04:00
parent 549629440d
commit 4a4498cd53
4 changed files with 10 additions and 8 deletions
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6
sim/rtlsim/Makefile
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@@ -34,7 +34,7 @@ SRCS += main.cpp simulator.cpp
ifdef AXI_BUS ifdef AXI_BUS
TOP = Vortex_axi TOP = Vortex_axi
CFLAGS += -DAXI_BUS CXXFLAGS += -DAXI_BUS
else else
TOP = Vortex TOP = Vortex
endif endif
@@ -44,9 +44,11 @@ VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic
VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO
VL_FLAGS += --x-initial unique --x-assign unique VL_FLAGS += --x-initial unique --x-assign unique
VL_FLAGS += verilator.vlt VL_FLAGS += verilator.vlt
VL_FLAGS += $(CONFIGS)
VL_FLAGS += $(RTL_INCLUDE) VL_FLAGS += $(RTL_INCLUDE)
VL_FLAGS += $(CONFIGS)
CXXFLAGS += $(CONFIGS)
# Debugigng # Debugigng
ifdef DEBUG ifdef DEBUG
VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS) VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS)

3
sim/rtlsim/simulator.cpp
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@@ -219,6 +219,7 @@ void Simulator::reset_axi_bus() {
vl_obj_->device->m_axi_awready = 0; vl_obj_->device->m_axi_awready = 0;
vl_obj_->device->m_axi_arready = 0; vl_obj_->device->m_axi_arready = 0;
vl_obj_->device->m_axi_rvalid = 0; vl_obj_->device->m_axi_rvalid = 0;
vl_obj_->device->m_axi_bvalid = 0;
} }
void Simulator::eval_axi_bus(bool clk) { void Simulator::eval_axi_bus(bool clk) {
@@ -369,7 +370,7 @@ void Simulator::eval_axi_bus(bool clk) {
mem_req_t mem_req; mem_req_t mem_req;
mem_req.tag = vl_obj_->device->m_axi_arid; mem_req.tag = vl_obj_->device->m_axi_arid;
mem_req.addr = vl_obj_->device->m_axi_araddr; mem_req.addr = vl_obj_->device->m_axi_araddr;
ram_->read(vl_obj_->device->m_axi_araddr, MEM_BLOCK_SIZE, mem_req.block.data()); ram_->read(mem_req.block.data(), vl_obj_->device->m_axi_araddr, MEM_BLOCK_SIZE);
mem_req.cycles_left = MEM_LATENCY; mem_req.cycles_left = MEM_LATENCY;
mem_req.write = 0; mem_req.write = 0;
for (auto& rsp : mem_rsp_vec_[req_bank]) { for (auto& rsp : mem_rsp_vec_[req_bank]) {

1
sim/simX/Makefile
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@@ -4,6 +4,7 @@ CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors
CXXFLAGS += -fPIC -Wno-maybe-uninitialized CXXFLAGS += -fPIC -Wno-maybe-uninitialized
CXXFLAGS += -I. -I../common -I../../hw CXXFLAGS += -I. -I../common -I../../hw
CXXFLAGS += -I../common/softfloat/source/include CXXFLAGS += -I../common/softfloat/source/include
CXXFLAGS += $(CONFIGS)
LDFLAGS += ../common/softfloat/build/Linux-x86_64-GCC/softfloat.a LDFLAGS += ../common/softfloat/build/Linux-x86_64-GCC/softfloat.a

8
sim/vlsim/Makefile
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@@ -25,10 +25,6 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CACHE_REQ_INFO DBG_FLAGS += -DDBG_CACHE_REQ_INFO
CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1
CXXFLAGS += $(CONFIGS)
SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp
SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp
SRCS += fpga.cpp opae_sim.cpp SRCS += fpga.cpp opae_sim.cpp
@@ -44,9 +40,11 @@ VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic
VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO
VL_FLAGS += --x-initial unique --x-assign unique VL_FLAGS += --x-initial unique --x-assign unique
VL_FLAGS += verilator.vlt VL_FLAGS += verilator.vlt
VL_FLAGS += $(CONFIGS)
VL_FLAGS += $(RTL_INCLUDE) VL_FLAGS += $(RTL_INCLUDE)
VL_FLAGS += $(CONFIGS)
CXXFLAGS += $(CONFIGS)
# Enable Verilator multithreaded simulation # Enable Verilator multithreaded simulation
#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
#VL_FLAGS += --threads $(THREADS) #VL_FLAGS += --threads $(THREADS)