SCOPE update
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@@ -20,8 +20,8 @@ module VX_fpu_unit #(
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wire ready_out;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [`NUM_THREADS-1:0] rsp_thread_mask;
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wire [31:0] rsp_curr_PC;
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wire [`NUM_THREADS-1:0] rsp_tmask;
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wire [31:0] rsp_PC;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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@@ -45,8 +45,8 @@ module VX_fpu_unit #(
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.write_addr (tag_in),
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.read_addr (tag_out),
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.release_addr (tag_out),
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.write_data ({fpu_req_if.wid, fpu_req_if.thread_mask, fpu_req_if.curr_PC, fpu_req_if.rd, fpu_req_if.wb}),
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.read_data ({rsp_wid, rsp_thread_mask, rsp_curr_PC, rsp_rd, rsp_wb}),
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.write_data ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.rd, fpu_req_if.wb}),
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.read_data ({rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb}),
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.release_slot (fpuq_pop),
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.full (fpuq_full)
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);
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@@ -131,8 +131,8 @@ module VX_fpu_unit #(
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.reset (reset),
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.stall (stall_out),
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.flush (1'b0),
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.in ({valid_out, rsp_wid, rsp_thread_mask, rsp_curr_PC, rsp_rd, rsp_wb, result, has_fflags, fflags}),
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.out ({fpu_commit_if.valid, fpu_commit_if.wid, fpu_commit_if.thread_mask, fpu_commit_if.curr_PC, fpu_commit_if.rd, fpu_commit_if.wb, fpu_commit_if.data, fpu_commit_if.has_fflags, fpu_commit_if.fflags})
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.in ({valid_out, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, result, has_fflags, fflags}),
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.out ({fpu_commit_if.valid, fpu_commit_if.wid, fpu_commit_if.tmask, fpu_commit_if.PC, fpu_commit_if.rd, fpu_commit_if.wb, fpu_commit_if.data, fpu_commit_if.has_fflags, fpu_commit_if.fflags})
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);
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assign ready_out = ~stall_out;
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