Proper SIMT with fine-grain scheduler implemented

rtl/VX_context.v

@@ -4,6 +4,7 @@
 module VX_context (
   input wire        clk,
   input wire        in_warp,
+  input wire        in_wb_warp,
   input wire        in_valid[`NT_M1:0],
   input wire        in_write_register,
   input wire[4:0]   in_rd,
@@ -20,18 +21,26 @@ module VX_context (
 
   output reg[31:0]   out_a_reg_data[`NT_M1:0],
   output reg[31:0]   out_b_reg_data[`NT_M1:0],
-  output wire        out_clone_stall
+  output wire        out_clone_stall,
+  output wire[31:0]  w0_t0_registers[31:0]
 	
 );
+		reg[5:0] state_stall;
+		initial begin
+			state_stall = 0;
+		end
+
 		wire[31:0] rd1_register[`NT_M1:0];
 		wire[31:0] rd2_register[`NT_M1:0];
 		/* verilator lint_off UNUSED */
 		wire[31:0] clone_regsiters[31:0];
 		/* verilator lint_on UNUSED */
+
+		assign w0_t0_registers = clone_regsiters;
 		
 		VX_register_file vx_register_file_master(
 			.clk               (clk),
-			.in_warp           (in_warp),
+			.in_wb_warp        (in_wb_warp),
 			.in_valid          (in_valid[0]),
 			.in_write_register (in_write_register),
 			.in_rd             (in_rd),
@@ -52,6 +61,7 @@ module VX_context (
 			VX_register_file_slave vx_register_file_slave(
 				.clk               (clk),
 				.in_warp           (in_warp),
+				.in_wb_warp        (in_wb_warp),
 				.in_valid          (in_valid[index]),
 				.in_write_register (in_write_register),
 				.in_rd             (in_rd),
@@ -64,11 +74,10 @@ module VX_context (
 				.out_src1_data     (rd1_register[index]),
 				.out_src2_data     (rd2_register[index])
 			);
-		  end  
+		  end
 		endgenerate
 
 
-		reg[5:0] state_stall = 0;
 		always @(posedge clk) begin
 			if ((in_is_clone) && state_stall == 0) begin
 				state_stall <= 10;