From 47c323465962b45229a6d6bee6d142a2e880d46a Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sun, 13 Jun 2021 10:58:48 -0700 Subject: [PATCH] minor update --- hw/rtl/VX_csr_io_arb.v | 71 -------------------------- hw/rtl/VX_instr_demux.v | 10 ++-- hw/rtl/VX_mem_unit.v | 25 ++++----- hw/rtl/cache/VX_bank.v | 2 +- hw/rtl/cache/VX_cache_core_rsp_merge.v | 4 +- hw/rtl/libs/VX_skid_buffer.v | 4 +- hw/syn/opae/Makefile | 8 +-- hw/syn/opae/setup16.cfg | 7 +++ hw/syn/opae/setup8.cfg | 7 +++ hw/syn/opae/vortex_afu16.json | 5 +- hw/syn/opae/vortex_afu8.json | 5 +- 11 files changed, 39 insertions(+), 109 deletions(-) delete mode 100644 hw/rtl/VX_csr_io_arb.v create mode 100644 hw/syn/opae/setup16.cfg create mode 100644 hw/syn/opae/setup8.cfg diff --git a/hw/rtl/VX_csr_io_arb.v b/hw/rtl/VX_csr_io_arb.v deleted file mode 100644 index d1e33451..00000000 --- a/hw/rtl/VX_csr_io_arb.v +++ /dev/null @@ -1,71 +0,0 @@ -`include "VX_define.vh" - -module VX_csr_io_arb ( - input wire clk, - input wire reset, - - // bus select - input wire select_io_rsp, - - // input requets - VX_csr_req_if csr_core_req_if, - VX_csr_io_req_if csr_io_req_if, - - // output request - VX_csr_pipe_req_if csr_pipe_req_if, - - // input response - VX_commit_if csr_pipe_rsp_if, - - // outputs responses - VX_commit_if csr_commit_if, - VX_csr_io_rsp_if csr_io_rsp_if -); - `UNUSED_VAR (clk) - `UNUSED_VAR (reset) - - wire [31:0] csr_core_req_data = csr_core_req_if.use_imm ? 32'(csr_core_req_if.rs1) : csr_core_req_if.rs1_data; - - // requests - assign csr_pipe_req_if.valid = csr_core_req_if.valid || csr_io_req_if.valid; - assign csr_pipe_req_if.wid = csr_core_req_if.wid; - assign csr_pipe_req_if.tmask = csr_core_req_if.tmask; - assign csr_pipe_req_if.PC = csr_core_req_if.PC; - assign csr_pipe_req_if.op_type = csr_core_req_if.valid ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS); - assign csr_pipe_req_if.addr = csr_core_req_if.valid ? csr_core_req_if.addr : csr_io_req_if.addr; - assign csr_pipe_req_if.data = csr_core_req_if.valid ? csr_core_req_data : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0); - assign csr_pipe_req_if.rd = csr_core_req_if.rd; - assign csr_pipe_req_if.wb = csr_core_req_if.wb; - assign csr_pipe_req_if.is_io = !csr_core_req_if.valid; - - // core always takes priority over IO bus - assign csr_core_req_if.ready = csr_pipe_req_if.ready; - assign csr_io_req_if.ready = csr_pipe_req_if.ready && !csr_core_req_if.valid; - - // responses - wire csr_io_rsp_ready; - VX_skid_buffer #( - .DATAW (32) - ) csr_io_out_buffer ( - .clk (clk), - .reset (reset), - .valid_in (csr_pipe_rsp_if.valid & select_io_rsp), - .data_in (csr_pipe_rsp_if.data[0]), - .ready_in (csr_io_rsp_ready), - .valid_out (csr_io_rsp_if.valid), - .data_out (csr_io_rsp_if.data), - .ready_out (csr_io_rsp_if.ready) - ); - - assign csr_commit_if.valid = csr_pipe_rsp_if.valid & ~select_io_rsp; - assign csr_commit_if.wid = csr_pipe_rsp_if.wid; - assign csr_commit_if.tmask = csr_pipe_rsp_if.tmask; - assign csr_commit_if.PC = csr_pipe_rsp_if.PC; - assign csr_commit_if.rd = csr_pipe_rsp_if.rd; - assign csr_commit_if.wb = csr_pipe_rsp_if.wb; - assign csr_commit_if.eop = csr_pipe_rsp_if.eop; - assign csr_commit_if.data = csr_pipe_rsp_if.data; - - assign csr_pipe_rsp_if.ready = select_io_rsp ? csr_io_rsp_ready : csr_commit_if.ready; - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_instr_demux.v b/hw/rtl/VX_instr_demux.v index 85f0bbf5..1bf8711b 100644 --- a/hw/rtl/VX_instr_demux.v +++ b/hw/rtl/VX_instr_demux.v @@ -39,7 +39,7 @@ module VX_instr_demux ( VX_skid_buffer #( .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BITS + `MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)), - .BUFFERED (1) + .USE_FASTREG (1) ) alu_buffer ( .clk (clk), .reset (reset), @@ -57,7 +57,7 @@ module VX_instr_demux ( VX_skid_buffer #( .DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)), - .BUFFERED (1) + .USE_FASTREG (1) ) lsu_buffer ( .clk (clk), .reset (reset), @@ -75,7 +75,7 @@ module VX_instr_demux ( VX_skid_buffer #( .DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32), - .BUFFERED (1) + .USE_FASTREG (1) ) csr_buffer ( .clk (clk), .reset (reset), @@ -94,7 +94,7 @@ module VX_instr_demux ( VX_skid_buffer #( .DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)), - .BUFFERED (1) + .USE_FASTREG (1) ) fpu_buffer ( .clk (clk), .reset (reset), @@ -116,7 +116,7 @@ module VX_instr_demux ( VX_skid_buffer #( .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32)), - .BUFFERED (1) + .USE_FASTREG (1) ) gpu_buffer ( .clk (clk), .reset (reset), diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index 888f4976..7db13e3c 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -256,26 +256,19 @@ module VX_mem_unit # ( ); end else begin // core to D-cache request - for (genvar i = 0; i < `DNUM_REQS; ++i) begin - VX_skid_buffer #( - .DATAW (`DCORE_ADDR_WIDTH + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH) - ) core_req_buf ( - .clk (clk), - .reset (reset), - .valid_in (dcache_core_req_if.valid[i]), - .data_in ({dcache_core_req_if.addr[i], dcache_core_req_if.rw[i], dcache_core_req_if.byteen[i], dcache_core_req_if.data[i], dcache_core_req_if.tag[i]}), - .ready_in (dcache_core_req_if.ready[i]), - .valid_out (dcache_req_if.valid[i]), - .data_out ({dcache_req_if.addr[i], dcache_req_if.rw[i], dcache_req_if.byteen[i], dcache_req_if.data[i], dcache_req_if.tag[i]}), - .ready_out (dcache_req_if.ready[i]) - ); - end + assign dcache_req_if.valid = dcache_core_req_if.valid; + assign dcache_req_if.addr = dcache_core_req_if.addr; + assign dcache_req_if.rw = dcache_core_req_if.rw; + assign dcache_req_if.byteen = dcache_core_req_if.byteen; + assign dcache_req_if.data = dcache_core_req_if.data; + assign dcache_req_if.tag = dcache_core_req_if.tag; + assign dcache_core_req_if.ready = dcache_req_if.ready; // D-cache to core reponse assign dcache_core_rsp_if.valid = dcache_rsp_if.valid; assign dcache_core_rsp_if.tag = dcache_rsp_if.tag; assign dcache_core_rsp_if.data = dcache_rsp_if.data; - assign dcache_rsp_if.ready = dcache_core_rsp_if.ready; + assign dcache_rsp_if.ready = dcache_core_rsp_if.ready; end wire [`DMEM_TAG_WIDTH-1:0] icache_mem_req_tag = `DMEM_TAG_WIDTH'(icache_mem_req_if.tag); @@ -289,7 +282,7 @@ module VX_mem_unit # ( .ADDR_WIDTH (`DMEM_ADDR_WIDTH), .TAG_IN_WIDTH (`DMEM_TAG_WIDTH), .BUFFERED_REQ (1), - .BUFFERED_RSP (0) + .BUFFERED_RSP (1) ) mem_arb ( .clk (clk), .reset (reset), diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 590ee91d..5f1b80d3 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -476,7 +476,7 @@ module VX_bank #( VX_skid_buffer #( .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS), - .BUFFERED (NUM_BANKS == 1) + .USE_FASTREG (NUM_BANKS == 1) ) core_rsp_req ( .clk (clk), .reset (reset), diff --git a/hw/rtl/cache/VX_cache_core_rsp_merge.v b/hw/rtl/cache/VX_cache_core_rsp_merge.v index 1254be81..1ffbaa23 100644 --- a/hw/rtl/cache/VX_cache_core_rsp_merge.v +++ b/hw/rtl/cache/VX_cache_core_rsp_merge.v @@ -107,7 +107,7 @@ module VX_cache_core_rsp_merge #( VX_skid_buffer #( .DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)), - .BUFFERED (1) + .USE_FASTREG (1) ) pipe_reg ( .clk (clk), .reset (reset), @@ -156,7 +156,7 @@ module VX_cache_core_rsp_merge #( for (genvar i = 0; i < NUM_REQS; i++) begin VX_skid_buffer #( .DATAW (CORE_TAG_WIDTH + `WORD_WIDTH), - .BUFFERED (1) + .USE_FASTREG (1) ) pipe_reg ( .clk (clk), .reset (reset), diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v index 31d789a0..e770a852 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -4,7 +4,7 @@ module VX_skid_buffer #( parameter DATAW = 1, parameter PASSTHRU = 0, parameter NOBACKPRESSURE = 0, - parameter BUFFERED = 0 + parameter USE_FASTREG = 0 ) ( input wire clk, input wire reset, @@ -50,7 +50,7 @@ module VX_skid_buffer #( end else begin - if (BUFFERED) begin + if (USE_FASTREG) begin reg [DATAW-1:0] data_out_r; reg [DATAW-1:0] buffer; diff --git a/hw/syn/opae/Makefile b/hw/syn/opae/Makefile index 4a35b54d..10034c00 100644 --- a/hw/syn/opae/Makefile +++ b/hw/syn/opae/Makefile @@ -76,16 +76,16 @@ $(FPGA_BUILD_DIR)_4c/build/dcp.qpf: afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_4c $(FPGA_BUILD_DIR)_8c/build/dcp.qpf: - afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_8c + afu_synth_setup -s setup8.cfg $(FPGA_BUILD_DIR)_8c $(FPGA_BUILD_DIR)_16c/build/dcp.qpf: - afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_16c + afu_synth_setup -s setup16.cfg $(FPGA_BUILD_DIR)_16c $(FPGA_BUILD_DIR)_32c/build/dcp.qpf: - afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_32c + afu_synth_setup -s setup16.cfg $(FPGA_BUILD_DIR)_32c $(FPGA_BUILD_DIR)_64c/build/dcp.qpf: - afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_64c + afu_synth_setup -s setup16.cfg $(FPGA_BUILD_DIR)_64c gen-sources-1c: ./gen_sources.sh $(CFLAGS) $(CONFIG1) > sources.txt diff --git a/hw/syn/opae/setup16.cfg b/hw/syn/opae/setup16.cfg new file mode 100644 index 00000000..e29575ee --- /dev/null +++ b/hw/syn/opae/setup16.cfg @@ -0,0 +1,7 @@ ++define+SYNTHESIS ++define+QUARTUS + +vortex_afu16.json +QI:vortex_afu.qsf + +C:sources.txt \ No newline at end of file diff --git a/hw/syn/opae/setup8.cfg b/hw/syn/opae/setup8.cfg new file mode 100644 index 00000000..36c42484 --- /dev/null +++ b/hw/syn/opae/setup8.cfg @@ -0,0 +1,7 @@ ++define+SYNTHESIS ++define+QUARTUS + +vortex_afu8.json +QI:vortex_afu.qsf + +C:sources.txt \ No newline at end of file diff --git a/hw/syn/opae/vortex_afu16.json b/hw/syn/opae/vortex_afu16.json index 04700701..0e6dd4c9 100644 --- a/hw/syn/opae/vortex_afu16.json +++ b/hw/syn/opae/vortex_afu16.json @@ -18,10 +18,7 @@ "mmio-status": 18, "mmio-scope-read": 20, "mmio-scope-write": 22, - "mmio-csr-core": 24, - "mmio-csr-addr": 26, - "mmio-csr-data": 28, - "mmio-csr-read": 30, + "mmio-dev-caps": 24, "afu-top-interface": { diff --git a/hw/syn/opae/vortex_afu8.json b/hw/syn/opae/vortex_afu8.json index cef41fbf..e4583a37 100644 --- a/hw/syn/opae/vortex_afu8.json +++ b/hw/syn/opae/vortex_afu8.json @@ -18,10 +18,7 @@ "mmio-status": 18, "mmio-scope-read": 20, "mmio-scope-write": 22, - "mmio-csr-core": 24, - "mmio-csr-addr": 26, - "mmio-csr-data": 28, - "mmio-csr-read": 30, + "mmio-dev-caps": 24, "afu-top-interface": {