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MULTICORE WITH L2 WORKING

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This commit is contained in:
felsabbagh3
2020-03-09 01:17:11 -07:00
parent 24f20a2da4
commit 469334f23e
28 changed files with 642 additions and 557 deletions
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116
rtl/VX_cache/VX_cache.v
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@@ -9,13 +9,13 @@ module VX_cache
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
parameter WORD_SIZE_BYTES = 16,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
parameter FUNC_ID = 0,
parameter FUNC_ID = 3,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
@@ -51,15 +51,15 @@ module VX_cache
input wire reset,
// Req Info
input wire [NUMBER_REQUESTS-1:0] core_req_valid,
input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUMBER_REQUESTS-1:0][31:0] core_req_writedata,
input wire[2:0] core_req_mem_read,
input wire[2:0] core_req_mem_write,
input wire [NUMBER_REQUESTS-1:0] core_req_valid,
input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_writedata,
input wire[NUMBER_REQUESTS-1:0][2:0] core_req_mem_read,
input wire[NUMBER_REQUESTS-1:0][2:0] core_req_mem_write,
// Req meta
input wire [4:0] core_req_rd,
input wire [1:0] core_req_wb,
input wire [NUMBER_REQUESTS-1:0][1:0] core_req_wb,
input wire [`NW_M1:0] core_req_warp_num,
input wire [31:0] core_req_pc,
output wire delay_req,
@@ -70,14 +70,15 @@ module VX_cache
output wire [4:0] core_wb_req_rd,
output wire [1:0] core_wb_req_wb,
output wire [`NW_M1:0] core_wb_warp_num,
output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_readdata,
output wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata,
output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_pc,
output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_address,
// Dram Fill Response
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
input wire [`IBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
output wire dram_fill_accept,
// Dram request
@@ -86,20 +87,14 @@ module VX_cache
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire dram_req_because_of_wb,
output wire dram_snp_full,
// Snoop Req
input wire snp_req,
input wire[31:0] snp_req_addr,
// Lower Level Cache
input wire llvq_pop,
output wire[NUMBER_REQUESTS-1:0] llvq_valid,
output wire[NUMBER_REQUESTS-1:0][31:0] llvq_res_addr,
output wire[NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data
input wire[31:0] snp_req_addr
);
@@ -111,8 +106,9 @@ module VX_cache
wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd;
wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb;
wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num;
wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_data;
wire [NUMBER_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data;
wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_pc;
wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_address;
wire dfqq_full;
@@ -124,54 +120,15 @@ module VX_cache
wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req;
wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp;
wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data;
wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] per_bank_dram_wb_req_data;
wire[NUMBER_BANKS-1:0] per_bank_reqq_full;
wire[NUMBER_BANKS-1:0] per_bank_llvq_pop;
wire[NUMBER_BANKS-1:0] per_bank_llvq_valid;
wire[NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr;
wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data;
wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid;
assign delay_req = (|per_bank_reqq_full);
assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]];
VX_dcache_llv_resp_bank_sel #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (NUMBER_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUMBER_REQUESTS (NUMBER_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
)
VX_dcache_llv_resp_bank_sel
(
.per_bank_llvq_pop (per_bank_llvq_pop),
.per_bank_llvq_valid (per_bank_llvq_valid),
.per_bank_llvq_res_addr(per_bank_llvq_res_addr),
.per_bank_llvq_res_data(per_bank_llvq_res_data),
.per_bank_llvq_res_tid (per_bank_llvq_res_tid),
.llvq_pop (llvq_pop),
.llvq_valid (llvq_valid),
.llvq_res_addr (llvq_res_addr),
.llvq_res_data (llvq_res_data)
);
VX_cache_dram_req_arb #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
@@ -245,6 +202,7 @@ module VX_cache
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUMBER_REQUESTS (NUMBER_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
@@ -266,6 +224,7 @@ module VX_cache
.per_bank_wb_warp_num(per_bank_wb_warp_num),
.per_bank_wb_data (per_bank_wb_data),
.per_bank_wb_pop (per_bank_wb_pop),
.per_bank_wb_address (per_bank_wb_address),
.core_no_wb_slot (core_no_wb_slot),
.core_wb_valid (core_wb_valid),
@@ -273,6 +232,7 @@ module VX_cache
.core_wb_req_wb (core_wb_req_wb),
.core_wb_warp_num (core_wb_warp_num),
.core_wb_readdata (core_wb_readdata),
.core_wb_address (core_wb_address),
.core_wb_pc (core_wb_pc)
);
@@ -281,12 +241,12 @@ module VX_cache
for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin
wire [NUMBER_REQUESTS-1:0] curr_bank_valids;
wire [NUMBER_REQUESTS-1:0][31:0] curr_bank_addr;
wire [NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata;
wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_writedata;
wire [4:0] curr_bank_rd;
wire [1:0] curr_bank_wb;
wire [NUMBER_REQUESTS-1:0][1:0] curr_bank_wb;
wire [`NW_M1:0] curr_bank_warp_num;
wire [2:0] curr_bank_mem_read;
wire [2:0] curr_bank_mem_write;
wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_read;
wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_write;
wire [31:0] curr_bank_pc;
wire curr_bank_wb_pop;
@@ -296,11 +256,12 @@ module VX_cache
wire [4:0] curr_bank_wb_rd;
wire [1:0] curr_bank_wb_wb;
wire [`NW_M1:0] curr_bank_wb_warp_num;
wire [31:0] curr_bank_wb_data;
wire [`WORD_SIZE_RNG] curr_bank_wb_data;
wire [31:0] curr_bank_wb_address;
wire curr_bank_dram_fill_rsp;
wire [31:0] curr_bank_dram_fill_rsp_addr;
wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data;
wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data;
wire curr_bank_dram_fill_accept;
wire curr_bank_dfqq_full;
@@ -312,19 +273,13 @@ module VX_cache
wire curr_bank_dram_wb_queue_pop;
wire curr_bank_dram_wb_req;
wire[31:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] curr_bank_dram_wb_req_data;
wire curr_bank_snp_req;
wire[31:0] curr_bank_snp_req_addr;
wire curr_bank_reqq_full;
wire curr_bank_llvq_pop;
wire curr_bank_llvq_valid;
wire[31:0] curr_bank_llvq_res_addr;
wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_llvq_res_data;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] curr_bank_llvq_res_tid;
// Core Req
@@ -348,6 +303,7 @@ module VX_cache
assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num;
assign per_bank_wb_data [curr_bank] = curr_bank_wb_data;
assign per_bank_wb_pc [curr_bank] = curr_bank_wb_pc;
assign per_bank_wb_address [curr_bank] = curr_bank_wb_address;
// Dram fill request
assign curr_bank_dfqq_full = dfqq_full;
@@ -370,14 +326,6 @@ module VX_cache
// Snoop Request
assign curr_bank_snp_req = snp_req && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_snp_req_addr = snp_req_addr;
// LLVQ
assign curr_bank_llvq_pop = per_bank_llvq_pop[curr_bank];
assign per_bank_llvq_valid[curr_bank] = curr_bank_llvq_valid;
assign per_bank_llvq_res_data[curr_bank] = curr_bank_llvq_res_data;
assign per_bank_llvq_res_addr[curr_bank] = curr_bank_llvq_res_addr;
assign per_bank_llvq_res_tid[curr_bank] = curr_bank_llvq_res_tid;
VX_bank #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
@@ -424,6 +372,7 @@ module VX_cache
.bank_wb_warp_num (curr_bank_wb_warp_num),
.bank_wb_data (curr_bank_wb_data),
.bank_wb_pc (curr_bank_wb_pc),
.bank_wb_address (curr_bank_wb_address),
// Dram fill req
.dram_fill_req (curr_bank_dram_fill_req),
@@ -446,13 +395,8 @@ module VX_cache
// Snoop Request
.snp_req (curr_bank_snp_req),
.snp_req_addr (curr_bank_snp_req_addr),
.snp_req_addr (curr_bank_snp_req_addr)
.llvq_pop (curr_bank_llvq_pop),
.llvq_valid (curr_bank_llvq_valid),
.llvq_res_addr (curr_bank_llvq_res_addr),
.llvq_res_data (curr_bank_llvq_res_data),
.llvq_res_tid (curr_bank_llvq_res_tid)
);
end