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fixed FPU-CSR data dependence

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This commit is contained in:
Blaise Tine
2020-11-25 09:05:38 -08:00
parent 71b98b166c
commit 461be0880d
24 changed files with 191 additions and 187 deletions
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28
hw/simulate/Makefile
View File

@@ -29,9 +29,10 @@ SRCS += ../rtl/fp_cores/svdpi/float_dpi.cpp
all: build-s
CF += -std=c++11 -fms-extensions -I../..
CF += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors -I../..
#CF += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors -I../..
VF += --language 1800-2009 --assert -Wall -Wpedantic
VF += -O2 --language 1800-2009 --assert -Wall -Wpedantic
VF += -Wno-DECLFILENAME
VF += --x-initial unique --x-assign unique
VF += --exe $(SRCS) $(INCLUDE)
@@ -42,41 +43,44 @@ DBG += -DVCD_OUTPUT $(DBG_FLAGS)
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
OPT_FAST = "-Wno-aligned-new -Wmaybe-uninitialized"
OPT_SLOW = "-Wno-aligned-new -Wmaybe-uninitialized"
gen-s:
verilator $(VF) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG $(SINGLECORE)'
gen-sd:
verilator $(VF) -O0 $(SINGLECORE) -CFLAGS '$(CF) -O0 -g $(DBG) $(SINGLECORE)' --trace --trace-structs $(DBG)
verilator $(VF) $(SINGLECORE) -CFLAGS '$(CF) $(DBG) $(SINGLECORE)' --trace --trace-structs $(DBG)
gen-st:
verilator $(VF) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(SINGLECORE)' --threads $(THREADS)
verilator $(VF) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CF) -DNDEBUG $(SINGLECORE)' --threads $(THREADS)
gen-m:
verilator $(VF) -DNDEBUG $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)'
gen-md:
verilator $(VF) $(MULTICORE) -CFLAGS '$(CF) -O0 -g $(DBG) $(MULTICORE)' --trace --trace-structs $(DBG)
verilator $(VF) $(MULTICORE) -CFLAGS '$(CF) $(DBG) $(MULTICORE)' --trace --trace-structs $(DBG)
gen-mt:
verilator $(VF) -DNDEBUG $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS)
verilator $(VF) -DNDEBUG $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)' --threads $(THREADS)
build-s: gen-s
(cd obj_dir && make -j -f VVortex.mk)
make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
build-sd: gen-sd
(cd obj_dir && make -j -f VVortex.mk)
make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
build-st: gen-st
(cd obj_dir && make -j -f VVortex.mk)
make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
build-m: gen-m
(cd obj_dir && make -j -f VVortex.mk)
make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
build-md: gen-md
(cd obj_dir && make -j -f VVortex.mk)
make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
build-mt: gen-mt
(cd obj_dir && make -j -f VVortex.mk)
make OPT_FAST=$(OPT_FAST) OPT_SLOW=$(OPT_SLOW) -j -C obj_dir -f VVortex.mk
run: run-s

14
hw/simulate/simulator.cpp
View File

@@ -61,10 +61,6 @@ void Simulator::reset() {
print_bufs_.clear();
dram_rsp_vec_.clear();
dram_rsp_active_ = false;
snp_req_active_ = false;
csr_req_active_ = false;
snp_req_size_ = 0;
pending_snp_reqs_ = 0;
csr_rsp_value_ = nullptr;
@@ -95,10 +91,6 @@ void Simulator::step() {
vortex_->clk = 0;
this->eval();
dram_rsp_ready_ = vortex_->dram_rsp_ready;
snp_req_ready_ = vortex_->snp_req_ready;
csr_io_req_ready_ = vortex_->csr_io_req_ready;
vortex_->clk = 1;
this->eval();
@@ -140,7 +132,7 @@ void Simulator::eval_dram_bus() {
// send DRAM response
if (dram_rsp_active_
&& vortex_->dram_rsp_valid && dram_rsp_ready_) {
&& vortex_->dram_rsp_valid && vortex_->dram_rsp_ready) {
dram_rsp_active_ = false;
}
if (!dram_rsp_active_) {
@@ -213,7 +205,7 @@ void Simulator::eval_io_bus() {
void Simulator::eval_snp_bus() {
if (snp_req_active_) {
if (vortex_->snp_req_valid && snp_req_ready_) {
if (vortex_->snp_req_valid && vortex_->snp_req_ready) {
assert(snp_req_size_);
#ifdef DBG_PRINT_CACHE_SNP
std::cout << std::dec << timestamp << ": [sim] SNP Req: addr=" << std::hex << vortex_->snp_req_addr << " tag=" << vortex_->snp_req_tag << " remain=" << (snp_req_size_-1) << std::endl;
@@ -246,7 +238,7 @@ void Simulator::eval_snp_bus() {
void Simulator::eval_csr_bus() {
if (csr_req_active_) {
if (vortex_->csr_io_req_valid && csr_io_req_ready_) {
if (vortex_->csr_io_req_valid && vortex_->csr_io_req_ready) {
#ifndef NDEBUG
if (vortex_->csr_io_req_rw)
std::cout << std::dec << timestamp << ": [sim] CSR Wr Req: core=" << (int)vortex_->csr_io_req_coreid << ", addr=" << std::hex << vortex_->csr_io_req_addr << ", value=" << vortex_->csr_io_req_data << std::endl;

4
hw/simulate/simulator.h
View File

@@ -66,10 +66,6 @@ private:
std::list<dram_req_t> dram_rsp_vec_;
bool dram_rsp_active_;
bool dram_rsp_ready_;
bool snp_req_ready_;
bool csr_io_req_ready_;
bool snp_req_active_;
bool csr_req_active_;

26
hw/simulate/testbench.cpp
View File

@@ -3,10 +3,6 @@
#include <fstream>
#include <iomanip>
#define GREEN "\\033[32m"
#define RED "\\033[31m"
#define DEFAULT "\\033[39m"
#define ALL_TESTS
int main(int argc, char **argv) {
@@ -14,7 +10,7 @@ int main(int argc, char **argv) {
if (argc == 1) {
#ifdef ALL_TESTS
std::string tests[] = {
"../../../benchmarks/riscv_tests/isa/rv32ui-p-add.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-add.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-addi.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-and.hex",
"../../../benchmarks/riscv_tests/isa/rv32ui-p-andi.hex",
@@ -81,7 +77,7 @@ int main(int argc, char **argv) {
};
for (std::string test : tests) {
std::cout << DEFAULT << "\n---------------------------------------\n";
std::cout << "\n---------------------------------------\n";
std::cout << test << std::endl;
@@ -93,16 +89,15 @@ int main(int argc, char **argv) {
bool status = (1 == simulator.get_last_wb_value(3));
if (status) std::cout << GREEN << "Test Passed: " << test << std::endl;
if (!status) std::cout << RED << "Test Failed: " << test << std::endl;
std::cout << DEFAULT;
if (status) std::cout << "Passed: " << test << std::endl;
if (!status) std::cout << "Failed: " << test << std::endl;
passed = passed && status;
if (!passed)
break;
}
for (std::string test : tests_fp) {
std::cout << DEFAULT << "\n---------------------------------------\n";
std::cout << "\n---------------------------------------\n";
std::cout << test << std::endl;
@@ -114,18 +109,17 @@ int main(int argc, char **argv) {
bool status = (1 == simulator.get_last_wb_value(3));
if (status) std::cout << GREEN << "Test Passed: " << test << std::endl;
if (!status) std::cout << RED << "Test Failed: " << test << std::endl;
std::cout << DEFAULT;
if (status) std::cout << "Passed: " << test << std::endl;
if (!status) std::cout << "Failed: " << test << std::endl;
passed = passed && status;
if (!passed)
break;
}
std::cout << DEFAULT << "\n***************************************\n";
std::cout << "\n***************************************\n";
if (passed) std::cout << DEFAULT << "PASSED ALL TESTS\n";
if (!passed) std::cout << DEFAULT << "Failed one or more tests\n";
if (passed) std::cout << "PASSED ALL TESTS\n";
if (!passed) std::cout << "Failed one or more tests\n";
return !passed;