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fixed FPU-CSR data dependence

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This commit is contained in:
Blaise Tine
2020-11-25 09:05:38 -08:00
parent 71b98b166c
commit 461be0880d
24 changed files with 191 additions and 187 deletions
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2
hw/rtl/VX_alu_unit.v
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@@ -11,7 +11,7 @@ module VX_alu_unit #(
// Outputs
VX_branch_ctl_if branch_ctl_if,
VX_exu_to_cmt_if alu_commit_if
VX_commit_if alu_commit_if
);
reg [`NUM_THREADS-1:0][31:0] alu_result;
reg [`NUM_THREADS-1:0][31:0] add_result;

51
hw/rtl/VX_commit.v
View File

@@ -3,16 +3,16 @@
module VX_commit #(
parameter CORE_ID = 0
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// inputs
VX_exu_to_cmt_if alu_commit_if,
VX_exu_to_cmt_if lsu_commit_if,
VX_exu_to_cmt_if mul_commit_if,
VX_exu_to_cmt_if csr_commit_if,
VX_fpu_to_cmt_if fpu_commit_if,
VX_exu_to_cmt_if gpu_commit_if,
VX_commit_if alu_commit_if,
VX_commit_if lsu_commit_if,
VX_commit_if mul_commit_if,
VX_commit_if csr_commit_if,
VX_commit_if fpu_commit_if,
VX_commit_if gpu_commit_if,
// outputs
VX_writeback_if writeback_if,
@@ -52,39 +52,8 @@ module VX_commit #(
.count (commit_size)
);
fflags_t fflags;
always @(*) begin
fflags = 0;
for (integer i = 0; i < `NUM_THREADS; i++) begin
if (fpu_commit_if.tmask[i]) begin
fflags.NX |= fpu_commit_if.fflags[i].NX;
fflags.UF |= fpu_commit_if.fflags[i].UF;
fflags.OF |= fpu_commit_if.fflags[i].OF;
fflags.DZ |= fpu_commit_if.fflags[i].DZ;
fflags.NV |= fpu_commit_if.fflags[i].NV;
end
end
end
reg csr_update_r;
reg [`NW_BITS-1:0] wid_r;
reg [CMTW-1:0] commit_size_r;
reg has_fflags_r;
fflags_t fflags_r;
always @(posedge clk) begin
csr_update_r <= commit_fire;
wid_r <= fpu_commit_if.wid;
commit_size_r <= commit_size;
has_fflags_r <= fpu_commit_if.has_fflags;
fflags_r <= fflags;
end
assign cmt_to_csr_if.valid = csr_update_r;
assign cmt_to_csr_if.wid = wid_r;
assign cmt_to_csr_if.commit_size = commit_size_r;
assign cmt_to_csr_if.has_fflags = has_fflags_r;
assign cmt_to_csr_if.fflags = fflags_r;
assign cmt_to_csr_if.valid = commit_fire;
assign cmt_to_csr_if.commit_size = commit_size;
// Writeback

4
hw/rtl/VX_csr_arb.v
View File

@@ -9,10 +9,10 @@ module VX_csr_arb (
VX_csr_req_if csr_req_if,
// input
VX_exu_to_cmt_if csr_rsp_if,
VX_commit_if csr_rsp_if,
// outputs
VX_exu_to_cmt_if csr_commit_if,
VX_commit_if csr_commit_if,
VX_csr_io_rsp_if csr_io_rsp_if,
input wire select_io_req,

10
hw/rtl/VX_csr_data.v
View File

@@ -7,7 +7,7 @@ module VX_csr_data #(
input wire reset,
VX_cmt_to_csr_if cmt_to_csr_if,
VX_csr_to_fpu_if csr_to_fpu_if,
VX_fpu_to_csr_if fpu_to_csr_if,
input wire read_enable,
input wire[`CSR_ADDR_BITS-1:0] read_addr,
@@ -40,9 +40,9 @@ module VX_csr_data #(
reg [31:0] read_data_r;
always @(posedge clk) begin
if (cmt_to_csr_if.valid && cmt_to_csr_if.has_fflags) begin
csr_fflags[cmt_to_csr_if.wid] <= cmt_to_csr_if.fflags;
csr_fcsr[cmt_to_csr_if.wid][`FFG_BITS-1:0] <= cmt_to_csr_if.fflags;
if (fpu_to_csr_if.write_enable) begin
csr_fflags[fpu_to_csr_if.write_wid] <= fpu_to_csr_if.write_fflags;
csr_fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0] <= fpu_to_csr_if.write_fflags;
end
if (write_enable) begin
@@ -144,6 +144,6 @@ module VX_csr_data #(
end
assign read_data = read_data_r;
assign csr_to_fpu_if.frm = csr_frm[csr_to_fpu_if.wid];
assign fpu_to_csr_if.read_frm = csr_frm[fpu_to_csr_if.read_wid];
endmodule

33
hw/rtl/VX_csr_unit.v
View File

@@ -7,18 +7,20 @@ module VX_csr_unit #(
input wire reset,
VX_cmt_to_csr_if cmt_to_csr_if,
VX_csr_to_fpu_if csr_to_fpu_if,
VX_fpu_to_csr_if fpu_to_csr_if,
VX_csr_io_req_if csr_io_req_if,
VX_csr_io_rsp_if csr_io_rsp_if,
VX_csr_req_if csr_req_if,
VX_exu_to_cmt_if csr_commit_if,
VX_commit_if csr_commit_if,
input wire busy
input wire busy,
input wire[`NUM_WARPS-1:0] fpu_pending,
output wire[`NUM_WARPS-1:0] pending
);
VX_csr_req_if csr_pipe_req_if();
VX_exu_to_cmt_if csr_pipe_rsp_if();
VX_csr_req_if csr_pipe_req_if();
VX_commit_if csr_pipe_rsp_if();
wire select_io_req = csr_io_req_if.valid;
wire select_io_rsp;
@@ -47,7 +49,7 @@ module VX_csr_unit #(
.clk (clk),
.reset (reset),
.cmt_to_csr_if (cmt_to_csr_if),
.csr_to_fpu_if (csr_to_fpu_if),
.fpu_to_csr_if (fpu_to_csr_if),
.read_enable (csr_pipe_req_if.valid),
.read_addr (csr_pipe_req_if.csr_addr),
.read_wid (csr_pipe_req_if.wid),
@@ -90,7 +92,8 @@ module VX_csr_unit #(
wire csr_we_s0 = csr_we_s0_unqual && csr_pipe_req_if.valid;
wire stall = ~csr_pipe_rsp_if.ready && csr_pipe_rsp_if.valid;
wire stall = (~csr_pipe_rsp_if.ready && csr_pipe_rsp_if.valid)
|| fpu_pending[csr_pipe_req_if.wid];
VX_generic_register #(
.N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1 + `CSR_ADDR_BITS + 1 + 32 + 32)
@@ -112,4 +115,20 @@ module VX_csr_unit #(
// can accept new request?
assign csr_pipe_req_if.ready = ~stall;
// pending request
reg [`NUM_WARPS-1:0] pending_r;
always @(posedge clk) begin
if (reset) begin
pending_r <= 0;
end else begin
if (csr_pipe_rsp_if.valid && csr_pipe_rsp_if.ready) begin
pending_r[csr_pipe_rsp_if.wid] <= 0;
end
if (csr_pipe_req_if.valid && csr_pipe_req_if.ready) begin
pending_r[csr_pipe_req_if.wid] <= 1;
end
end
end
assign pending = pending_r;
endmodule

26
hw/rtl/VX_execute.v
View File

@@ -30,17 +30,19 @@ module VX_execute #(
// outputs
VX_branch_ctl_if branch_ctl_if,
VX_warp_ctl_if warp_ctl_if,
VX_exu_to_cmt_if alu_commit_if,
VX_exu_to_cmt_if lsu_commit_if,
VX_exu_to_cmt_if csr_commit_if,
VX_exu_to_cmt_if mul_commit_if,
VX_fpu_to_cmt_if fpu_commit_if,
VX_exu_to_cmt_if gpu_commit_if,
VX_commit_if alu_commit_if,
VX_commit_if lsu_commit_if,
VX_commit_if csr_commit_if,
VX_commit_if mul_commit_if,
VX_commit_if fpu_commit_if,
VX_commit_if gpu_commit_if,
input wire busy,
output wire ebreak
);
VX_csr_to_fpu_if csr_to_fpu_if();
VX_fpu_to_csr_if fpu_to_csr_if();
wire[`NUM_WARPS-1:0] csr_pending;
wire[`NUM_WARPS-1:0] fpu_pending;
VX_alu_unit #(
.CORE_ID(CORE_ID)
@@ -70,11 +72,13 @@ module VX_execute #(
.clk (clk),
.reset (reset),
.cmt_to_csr_if (cmt_to_csr_if),
.csr_to_fpu_if (csr_to_fpu_if),
.fpu_to_csr_if (fpu_to_csr_if),
.csr_io_req_if (csr_io_req_if),
.csr_io_rsp_if (csr_io_rsp_if),
.csr_req_if (csr_req_if),
.csr_commit_if (csr_commit_if),
.fpu_pending (fpu_pending),
.pending (csr_pending),
.busy (busy)
);
@@ -105,8 +109,10 @@ module VX_execute #(
.clk (clk),
.reset (reset),
.fpu_req_if (fpu_req_if),
.csr_to_fpu_if (csr_to_fpu_if),
.fpu_commit_if (fpu_commit_if)
.fpu_to_csr_if (fpu_to_csr_if),
.fpu_commit_if (fpu_commit_if),
.csr_pending (csr_pending),
.pending (fpu_pending)
);
`else
assign fpu_req_if.ready = 0;

65
hw/rtl/VX_fpu_unit.v
View File

@@ -9,10 +9,13 @@ module VX_fpu_unit #(
// inputs
VX_fpu_req_if fpu_req_if,
VX_csr_to_fpu_if csr_to_fpu_if,
// outputs
VX_fpu_to_cmt_if fpu_commit_if
// outputs
VX_fpu_to_csr_if fpu_to_csr_if,
VX_commit_if fpu_commit_if,
input wire[`NUM_WARPS-1:0] csr_pending,
output wire[`NUM_WARPS-1:0] pending
);
localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE);
@@ -53,13 +56,13 @@ module VX_fpu_unit #(
);
// can accept new request?
assign fpu_req_if.ready = ready_in && ~fpuq_full;
assign fpu_req_if.ready = ready_in && ~fpuq_full && !csr_pending[fpu_req_if.wid];
wire valid_in = fpu_req_if.valid && ~fpuq_full;
wire valid_in = fpu_req_if.valid && ~fpuq_full && !csr_pending[fpu_req_if.wid];
// resolve dynamic FRM
assign csr_to_fpu_if.wid = fpu_req_if.wid;
wire [`FRM_BITS-1:0] fpu_frm = (fpu_req_if.op_mod == `FRM_DYN) ? csr_to_fpu_if.frm : fpu_req_if.op_mod;
// resolve dynamic FRM from CSR
assign fpu_to_csr_if.read_wid = fpu_req_if.wid;
wire [`FRM_BITS-1:0] fpu_frm = (fpu_req_if.op_mod == `FRM_DYN) ? fpu_to_csr_if.read_frm : fpu_req_if.op_mod;
`ifdef FPU_FAST
@@ -127,19 +130,57 @@ module VX_fpu_unit #(
`endif
wire stall_out = ~fpu_commit_if.ready && fpu_commit_if.valid;
reg has_fflags_r;
fflags_t fflags_r;
fflags_t rsp_fflags;
always @(*) begin
rsp_fflags = 0;
for (integer i = 0; i < `NUM_THREADS; i++) begin
if (rsp_tmask[i]) begin
rsp_fflags.NX |= fflags[i].NX;
rsp_fflags.UF |= fflags[i].UF;
rsp_fflags.OF |= fflags[i].OF;
rsp_fflags.DZ |= fflags[i].DZ;
rsp_fflags.NV |= fflags[i].NV;
end
end
end
wire stall_out = ~fpu_commit_if.ready && fpu_commit_if.valid;
VX_generic_register #(
.N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + (`NUM_THREADS * `FFG_BITS))
.N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `FFG_BITS)
) pipe_reg (
.clk (clk),
.reset (reset),
.stall (stall_out),
.flush (1'b0),
.in ({valid_out, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, result, has_fflags, fflags}),
.out ({fpu_commit_if.valid, fpu_commit_if.wid, fpu_commit_if.tmask, fpu_commit_if.PC, fpu_commit_if.rd, fpu_commit_if.wb, fpu_commit_if.data, fpu_commit_if.has_fflags, fpu_commit_if.fflags})
.in ({valid_out, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, result, has_fflags, rsp_fflags}),
.out ({fpu_commit_if.valid, fpu_commit_if.wid, fpu_commit_if.tmask, fpu_commit_if.PC, fpu_commit_if.rd, fpu_commit_if.wb, fpu_commit_if.data, has_fflags_r, fflags_r})
);
assign ready_out = ~stall_out;
// CSR fflags Update
assign fpu_to_csr_if.write_enable = fpu_commit_if.valid && fpu_commit_if.ready && has_fflags_r;
assign fpu_to_csr_if.write_wid = fpu_commit_if.wid;
assign fpu_to_csr_if.write_fflags = fflags_r;
// pending request
reg [`NUM_WARPS-1:0] pending_r;
always @(posedge clk) begin
if (reset) begin
pending_r <= 0;
end else begin
if (fpu_commit_if.valid && fpu_commit_if.ready) begin
pending_r[fpu_commit_if.wid] <= 0;
end
if (fpu_req_if.valid && fpu_req_if.ready) begin
pending_r[fpu_req_if.wid] <= 1;
end
end
end
assign pending = pending_r;
endmodule

10
hw/rtl/VX_gpu_unit.v
View File

@@ -5,15 +5,15 @@ module VX_gpu_unit #(
) (
`SCOPE_IO_VX_gpu_unit
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// Inputs
VX_gpu_req_if gpu_req_if,
VX_gpu_req_if gpu_req_if,
// Outputs
VX_warp_ctl_if warp_ctl_if,
VX_exu_to_cmt_if gpu_commit_if
VX_warp_ctl_if warp_ctl_if,
VX_commit_if gpu_commit_if
);
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)

4
hw/rtl/VX_lsu_unit.v
View File

@@ -13,10 +13,10 @@ module VX_lsu_unit #(
VX_cache_core_rsp_if dcache_rsp_if,
// inputs
VX_lsu_req_if lsu_req_if,
VX_lsu_req_if lsu_req_if,
// outputs
VX_exu_to_cmt_if lsu_commit_if
VX_commit_if lsu_commit_if
);
wire [`NUM_THREADS-1:0] req_tmask;
wire req_rw;

4
hw/rtl/VX_mul_unit.v
View File

@@ -7,10 +7,10 @@ module VX_mul_unit #(
input wire reset,
// Inputs
VX_mul_req_if mul_req_if,
VX_mul_req_if mul_req_if,
// Outputs
VX_exu_to_cmt_if mul_commit_if
VX_commit_if mul_commit_if
);
localparam MULQ_BITS = `LOG2UP(`MULQ_SIZE);

12
hw/rtl/VX_pipeline.v
View File

@@ -112,12 +112,12 @@ module VX_pipeline #(
VX_writeback_if writeback_if();
VX_wstall_if wstall_if();
VX_join_if join_if();
VX_exu_to_cmt_if alu_commit_if();
VX_exu_to_cmt_if lsu_commit_if();
VX_exu_to_cmt_if csr_commit_if();
VX_exu_to_cmt_if mul_commit_if();
VX_fpu_to_cmt_if fpu_commit_if();
VX_exu_to_cmt_if gpu_commit_if();
VX_commit_if alu_commit_if();
VX_commit_if lsu_commit_if();
VX_commit_if csr_commit_if();
VX_commit_if mul_commit_if();
VX_commit_if fpu_commit_if();
VX_commit_if gpu_commit_if();
VX_fetch #(
.CORE_ID(CORE_ID)

18
hw/rtl/VX_writeback.v
View File

@@ -3,19 +3,19 @@
module VX_writeback #(
parameter CORE_ID = 0
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// inputs
VX_exu_to_cmt_if alu_commit_if,
VX_exu_to_cmt_if lsu_commit_if,
VX_exu_to_cmt_if csr_commit_if,
VX_exu_to_cmt_if mul_commit_if,
VX_fpu_to_cmt_if fpu_commit_if,
VX_exu_to_cmt_if gpu_commit_if,
VX_commit_if alu_commit_if,
VX_commit_if lsu_commit_if,
VX_commit_if csr_commit_if,
VX_commit_if mul_commit_if,
VX_commit_if fpu_commit_if,
VX_commit_if gpu_commit_if,
// outputs
VX_writeback_if writeback_if
VX_writeback_if writeback_if
);
wire alu_valid = alu_commit_if.valid && alu_commit_if.wb;
wire lsu_valid = lsu_commit_if.valid && lsu_commit_if.wb;

6
hw/rtl/interfaces/VX_cmt_to_csr_if.v
View File

@@ -5,12 +5,8 @@
interface VX_cmt_to_csr_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire valid;
wire [$clog2(`NUM_THREADS+1)-1:0] commit_size;
wire has_fflags;
fflags_t fflags;
endinterface

6
hw/rtl/interfaces/VX_exu_to_cmt_if.v → hw/rtl/interfaces/VX_commit_if.v
View File

@@ -1,9 +1,9 @@
`ifndef VX_EXU_TO_CMT_IF
`define VX_EXU_TO_CMT_IF
`ifndef VX_COMMIT_IF
`define VX_COMMIT_IF
`include "VX_define.vh"
interface VX_exu_to_cmt_if ();
interface VX_commit_if ();
wire valid;

17
hw/rtl/interfaces/VX_csr_to_fpu_if.v
View File

@@ -1,17 +0,0 @@
`ifndef VX_CSR_TO_FPU_IF
`define VX_CSR_TO_FPU_IF
`include "VX_define.vh"
`ifndef EXTF_F_ENABLE
`IGNORE_WARNINGS_BEGIN
`endif
interface VX_csr_to_fpu_if ();
wire [`NW_BITS-1:0] wid;
wire [`FRM_BITS-1:0] frm;
endinterface
`endif

17
hw/rtl/interfaces/VX_fpu_to_csr_if.v
View File

@@ -3,19 +3,14 @@
`include "VX_define.vh"
`ifndef EXTF_F_ENABLE
`IGNORE_WARNINGS_BEGIN
`endif
interface VX_fpu_to_csr_if ();
wire valid;
wire [`NW_BITS-1:0] wid;
wire fflags_NV;
wire fflags_DZ;
wire fflags_OF;
wire fflags_UF;
wire fflags_NX;
wire write_enable;
wire [`NW_BITS-1:0] write_wid;
fflags_t write_fflags;
wire [`NW_BITS-1:0] read_wid;
wire [`FRM_BITS-1:0] read_frm;
endinterface