RTL code refactoring

2020-04-20 10:21:06 -04:00
parent 0c81a3ae19
commit 45990e391f
4 changed files with 182 additions and 182 deletions
--- a/hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
+++ b/hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
@@ -13,7 +13,7 @@ interface VX_gpu_dcache_rsp_if #(
    wire [4:0]                     core_rsp_read;
    wire [1:0]                     core_rsp_write;
 `IGNORE_WARNINGS_END    
-    //wire [NUM_REQUESTS-1:0][31:0]  core_rsp_pc;    
+    wire [NUM_REQUESTS-1:0][31:0]  core_rsp_pc;    
    wire [NUM_REQUESTS-1:0][31:0]  core_rsp_data;
    wire                           core_rsp_ready;