wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

scope fixes

Browse Source
This commit is contained in:
Blaise Tine
2020-06-09 07:03:52 -07:00
parent 9575fe9a51
commit 457783322b
16 changed files with 349 additions and 155 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
hw/rtl/VX_define.vh
View File

@@ -297,7 +297,9 @@
scope_dram_rsp_valid, \
scope_dram_rsp_ready, \
scope_schedule_delay, \
scope_icache_req_addr, \
scope_icache_req_tag, \
scope_icache_rsp_data, \
scope_icache_rsp_tag, \
scope_dcache_req_tag, \
scope_dcache_rsp_tag, \
@@ -306,16 +308,18 @@
`define SCOPE_SIGNALS_DECL \
wire scope_icache_req_valid; \
wire [`DCORE_TAG_WIDTH-1:0] scope_icache_req_tag; \
wire [29:0] scope_icache_req_addr; \
wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag; \
wire scope_icache_req_ready; \
wire scope_icache_rsp_valid; \
wire [`DCORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \
wire [31:0] scope_icache_rsp_data; \
wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \
wire scope_icache_rsp_ready; \
wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid; \
wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \
wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \
wire scope_dcache_req_ready; \
wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid; \
wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \
wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \
wire scope_dcache_rsp_ready; \
wire scope_dram_req_valid; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag; \
@@ -325,48 +329,70 @@
wire scope_dram_rsp_ready; \
wire scope_schedule_delay;
`define SCOPE_SIGNALS_IO \
`define SCOPE_SIGNALS_ICACHE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire scope_icache_req_valid, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_icache_req_tag, \
output wire [29:0] scope_icache_req_addr, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag, \
output wire scope_icache_req_ready, \
output wire scope_icache_rsp_valid, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_icache_rsp_tag, \
output wire [31:0] scope_icache_rsp_data, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag, \
output wire scope_icache_rsp_ready, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_DCACHE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \
output wire scope_dcache_req_ready, \
output wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \
output wire scope_dcache_rsp_ready, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_DRAM_IO \
/* verilator lint_off UNDRIVEN */ \
output wire scope_dram_req_valid, \
output wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag, \
output wire scope_dram_req_ready, \
output wire scope_dram_rsp_valid, \
output wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag, \
output wire scope_dram_rsp_ready, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_CORE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire scope_schedule_delay, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_ATTACH \
`define SCOPE_SIGNALS_ICACHE_ATTACH \
.scope_icache_req_valid (scope_icache_req_valid), \
.scope_icache_req_addr (scope_icache_req_addr), \
.scope_icache_req_tag (scope_icache_req_tag), \
.scope_icache_req_ready (scope_icache_req_ready), \
.scope_icache_rsp_valid (scope_icache_rsp_valid), \
.scope_icache_rsp_data (scope_icache_rsp_data), \
.scope_icache_rsp_tag (scope_icache_rsp_tag), \
.scope_icache_rsp_ready (scope_icache_rsp_ready), \
.scope_icache_rsp_ready (scope_icache_rsp_ready),
`define SCOPE_SIGNALS_DCACHE_ATTACH \
.scope_dcache_req_valid (scope_dcache_req_valid), \
.scope_dcache_req_tag (scope_dcache_req_tag), \
.scope_dcache_req_ready (scope_dcache_req_ready), \
.scope_dcache_rsp_valid (scope_dcache_rsp_valid), \
.scope_dcache_rsp_tag (scope_dcache_rsp_tag), \
.scope_dcache_rsp_ready (scope_dcache_rsp_ready), \
.scope_dcache_rsp_ready (scope_dcache_rsp_ready),
`define SCOPE_SIGNALS_DRAM_ATTACH \
.scope_dram_req_valid (scope_dram_req_valid), \
.scope_dram_req_tag (scope_dram_req_tag), \
.scope_dram_req_ready (scope_dram_req_ready), \
.scope_dram_rsp_valid (scope_dram_rsp_valid), \
.scope_dram_rsp_tag (scope_dram_rsp_tag), \
.scope_dram_rsp_ready (scope_dram_rsp_ready), \
.scope_dram_rsp_ready (scope_dram_rsp_ready),
`define SCOPE_SIGNALS_CORE_ATTACH \
.scope_schedule_delay (scope_schedule_delay),
`define SCOPE_ASSIGN(d,s) assign d = s