minor update

hw/rtl/VX_csr_data.v

@@ -78,7 +78,7 @@ module VX_csr_data (
 
     assign read_csr_data =  read_cycle    ? cycle[31:0] :
                                 read_cycleh   ? cycle[63:32] :
-                                read_instret  ? instret[31:0] :
+                                    read_instret  ? instret[31:0] :
-                                read_instreth ? instret[63:32] :
+                                        read_instreth ? instret[63:32] :
-                                                {{20{1'b0}}, csr[read_addr]};
+                                            {{20{1'b0}}, csr[read_addr]};
 endmodule : VX_csr_data

hw/rtl/VX_scheduler.v

@@ -47,10 +47,9 @@ module VX_scheduler (
                          || (gpr_stage_delay && (is_mem || is_exec))
                          || (exec_delay && is_exec);
 
-    integer i;
+    integer i, w;
-    integer w;
-    always @(posedge clk) begin
 
+    always @(posedge clk) begin
         if (reset) begin
             for (w = 0; w < `NUM_WARPS; w=w+1) begin
                 for (i = 0; i < 32; i = i + 1) begin

hw/rtl/VX_warp_sched.v

@@ -88,7 +88,7 @@ module VX_warp_sched (
     wire wstall_this_cycle;
 
     reg[`NUM_THREADS-1:0] thread_masks[`NUM_WARPS-1:0];
-    reg[31:0]     warp_pcs[`NUM_WARPS-1:0];
+    reg[31:0] warp_pcs[`NUM_WARPS-1:0];
 
     // barriers
     reg[`NUM_WARPS-1:0] barrier_stall_mask[(`NUM_BARRIERS-1):0];

hw/rtl/cache/VX_cache_req_queue.v

@@ -173,7 +173,7 @@ module VX_cache_req_queue #(
 
     always @(posedge clk) begin
         if (reset) begin
-             use_per_valids   <= 0;
+            use_per_valids    <= 0;
             use_per_addr      <= 0;
             use_per_writedata <= 0;
             use_per_rd        <= 0;