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fixed lmp_mult parameters, ram init filepath

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This commit is contained in:
Blaise Tine
2020-09-04 07:51:46 -07:00
parent dccea80b68
commit 42e3b6c45d
36 changed files with 738 additions and 495 deletions
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51
hw/rtl/libs/VX_divide.v
View File

@@ -1,21 +1,18 @@
`include "VX_platform.vh"
module VX_divide #(
parameter WIDTHN = 1,
parameter WIDTHD = 1,
parameter WIDTHQ = 1,
parameter WIDTHR = 1,
parameter WIDTHN = 1,
parameter WIDTHD = 1,
parameter WIDTHQ = 1,
parameter WIDTHR = 1,
parameter NSIGNED = 0,
parameter DSIGNED = 0,
parameter PIPELINE = 0
parameter LATENCY = 0
) (
input wire clk,
input wire reset,
input wire clk_en,
input wire enable,
input wire [WIDTHN-1:0] numer,
input wire [WIDTHD-1:0] denom,
output wire [WIDTHQ-1:0] quotient,
output wire [WIDTHR-1:0] remainder
);
@@ -27,11 +24,11 @@ module VX_divide #(
lpm_divide divide (
.clock (clk),
.clken (enable),
.numer (numer),
.denom (denom),
.quotient (quotient_unqual),
.remain (remainder_unqual),
.clken (clk_en)
.remain (remainder_unqual)
);
defparam
@@ -41,7 +38,7 @@ module VX_divide #(
divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
divide.lpm_pipeline = PIPELINE;
divide.lpm_pipeline = LATENCY;
assign quotient = quotient_unqual [WIDTHQ-1:0];
assign remainder = remainder_unqual [WIDTHR-1:0];
@@ -72,34 +69,24 @@ module VX_divide #(
end
end
if (PIPELINE == 0) begin
if (LATENCY == 0) begin
assign quotient = quotient_unqual [WIDTHQ-1:0];
assign remainder = remainder_unqual [WIDTHR-1:0];
end else begin
reg [WIDTHN-1:0] quotient_pipe [0:PIPELINE-1];
reg [WIDTHD-1:0] remainder_pipe [0:PIPELINE-1];
reg [WIDTHN-1:0] quotient_pipe [0:LATENCY-1];
reg [WIDTHD-1:0] remainder_pipe [0:LATENCY-1];
for (genvar i = 0; i < PIPELINE; i++) begin
always @(posedge clk) begin
if (reset) begin
quotient_pipe[i] <= 0;
remainder_pipe[i] <= 0;
end else begin
if (clk_en) begin
if (i == 0) begin
quotient_pipe[i] <= quotient_unqual;
remainder_pipe[i] <= remainder_unqual;
end else begin
quotient_pipe[i] <= quotient_pipe[i-1];
remainder_pipe[i] <= remainder_pipe[i-1];
end
end
for (genvar i = 0; i < LATENCY; i++) begin
always @(posedge clk) begin
if (enable) begin
quotient_pipe[i] <= (0 == i) ? quotient_unqual : quotient_pipe[i-1];
remainder_pipe[i] <= (0 == i) ? remainder_unqual : remainder_pipe[i-1];
end
end
end
assign quotient = quotient_pipe[PIPELINE-1][WIDTHQ-1:0];
assign remainder = remainder_pipe[PIPELINE-1][WIDTHR-1:0];
assign quotient = quotient_pipe[LATENCY-1][WIDTHQ-1:0];
assign remainder = remainder_pipe[LATENCY-1][WIDTHR-1:0];
end
`endif

55
hw/rtl/libs/VX_multiplier.v
View File

@@ -1,16 +1,14 @@
`include "VX_platform.vh"
module VX_multiplier #(
parameter WIDTHA = 1,
parameter WIDTHB = 1,
parameter WIDTHP = 1,
parameter SIGNED = 0,
parameter PIPELINE = 0
parameter WIDTHA = 1,
parameter WIDTHB = 1,
parameter WIDTHP = 1,
parameter SIGNED = 0,
parameter LATENCY = 0
) (
input wire clk,
input wire reset,
input wire clk_en,
input wire clk,
input wire enable,
input wire [WIDTHA-1:0] dataa,
input wire [WIDTHB-1:0] datab,
output wire [WIDTHP-1:0] result
@@ -20,20 +18,22 @@ module VX_multiplier #(
lpm_mult mult (
.clock (clk),
.clken (enable),
.dataa (dataa),
.datab (datab),
.result (result),
.clken (clk_en),
.result (result),
.aclr (1'b0),
.sclr (1'b0),
.sum (1'b0)
);
defparam mult.lpm_type = "LPM_MULT",
defparam mult.lpm_type = "LPM_MULT",
mult.lpm_widtha = WIDTHA,
mult.lpm_widthb = WIDTHB,
mult.lpm_widthp = WIDTHP,
mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED",
mult.lpm_pipeline = PIPELINE,
mult.lpm_hint = "MAXIMIZE_SPEED=9,DEDICATED_MULTIPLIER_CIRCUITRY=YES";
mult.lpm_pipeline = LATENCY,
mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9";
`else
wire [WIDTHP-1:0] result_unqual;
@@ -44,29 +44,20 @@ module VX_multiplier #(
assign result_unqual = dataa * datab;
end
if (PIPELINE == 0) begin
if (LATENCY == 0) begin
assign result = result_unqual;
end else begin
reg [WIDTHP-1:0] result_pipe [0:PIPELINE-1];
end else begin
reg [WIDTHP-1:0] result_pipe [0:LATENCY-1];
for (genvar i = 0; i < PIPELINE; i++) begin
for (genvar i = 0; i < LATENCY; i++) begin
always @(posedge clk) begin
if (reset) begin
result_pipe[i] <= 0;
end else begin
if (clk_en) begin
if (i == 0) begin
result_pipe[i] <= result_unqual;
end else begin
result_pipe[i] <= result_pipe[i-1];
end
end
if (enable) begin
result_pipe[i] <= (0 == i) ? result_unqual : result_pipe[i-1];
end
end
end
assign result = result_pipe[PIPELINE-1];
end
assign result = result_pipe[LATENCY-1];
end
`endif