cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes

hw/rtl/libs/VX_axi_adapter.sv

@@ -125,7 +125,7 @@ module VX_axi_adapter #(
 
     // AXI write response channel
     `UNUSED_VAR (m_axi_bid);
-    `RUNTIME_ASSERT(~m_axi_bvalid || m_axi_bresp == 0, ("AXI response error"));
+    `RUNTIME_ASSERT(~m_axi_bvalid || m_axi_bresp == 0, ("%t: *** AXI response error", $time));
     assign m_axi_bready     = 1'b1;
 
     // AXI read request channel
@@ -144,7 +144,7 @@ module VX_axi_adapter #(
     assign mem_rsp_valid    = m_axi_rvalid;
     assign mem_rsp_tag      = m_axi_rid;
     assign mem_rsp_data     = m_axi_rdata;
-    `RUNTIME_ASSERT(~m_axi_rvalid || m_axi_rresp == 0, ("AXI response error"));
+    `RUNTIME_ASSERT(~m_axi_rvalid || m_axi_rresp == 0, ("%t: *** AXI response error", $time));
     `UNUSED_VAR (m_axi_rlast);
     assign m_axi_rready     = mem_rsp_ready;
 

hw/rtl/libs/VX_index_queue.sv

@@ -32,7 +32,7 @@ module VX_index_queue #(
     assign enqueue = push;       
     assign dequeue = !empty && !valid[rd_a]; // auto-remove when head is invalid
 
-    `RUNTIME_ASSERT(!push || !full, ("invalid inputs"));
+    `RUNTIME_ASSERT(!push || !full, ("%t: *** invalid inputs", $time));
     
     always @(posedge clk) begin
         if (reset) begin

hw/rtl/libs/VX_popcount.sv

@@ -4,12 +4,17 @@
 module VX_popcount #(
     parameter MODEL = 1,
     parameter N     = 1,
-    parameter LOGN  = $clog2(N),
-    parameter M     = LOGN+1    
+    parameter M     = $clog2(N+1) 
 ) (
     input  wire [N-1:0] in_i,
     output wire [M-1:0] cnt_o
 );
+`ifndef SYNTHESIS
+    assign cnt_o = $countones(in_i);
+`else
+`ifdef QUARTUS
+    assign cnt_o = $countones(in_i);
+`else
     if (N == 1) begin
 
         assign cnt_o = in_i;
@@ -53,6 +58,8 @@ module VX_popcount #(
         assign cnt_o = cnt_r;
     
     end
+`endif
+`endif
 
 endmodule
 `TRACING_ON

hw/rtl/libs/VX_skid_buffer.sv

@@ -30,7 +30,7 @@ module VX_skid_buffer #(
 
     end else if (NOBACKPRESSURE) begin
 
-        `RUNTIME_ASSERT(ready_out, ("ready_out should always be asserted"))
+        `RUNTIME_ASSERT(ready_out, ("%t: *** ready_out should always be asserted", $time))
 
         wire stall = valid_out && ~ready_out;