cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
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@@ -11,7 +11,7 @@ interface VX_perf_cache_if ();
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wire [`PERF_CTR_BITS-1:0] write_misses;
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wire [`PERF_CTR_BITS-1:0] bank_stalls;
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wire [`PERF_CTR_BITS-1:0] mshr_stalls;
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wire [`PERF_CTR_BITS-1:0] pipe_stalls;
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wire [`PERF_CTR_BITS-1:0] mem_stalls;
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wire [`PERF_CTR_BITS-1:0] crsp_stalls;
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modport master (
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@@ -21,7 +21,7 @@ interface VX_perf_cache_if ();
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output write_misses,
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output bank_stalls,
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output mshr_stalls,
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output pipe_stalls,
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output mem_stalls,
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output crsp_stalls
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);
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@@ -32,7 +32,7 @@ interface VX_perf_cache_if ();
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input write_misses,
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input bank_stalls,
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input mshr_stalls,
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input pipe_stalls,
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input mem_stalls,
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input crsp_stalls
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);
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