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cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes

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This commit is contained in:
Blaise Tine
2021-11-30 07:08:15 -05:00
parent b995843a5b
commit 41d7e6c63a
79 changed files with 2148 additions and 1372 deletions
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5
hw/rtl/interfaces/VX_alu_req_if.sv
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@@ -5,7 +5,8 @@
interface VX_alu_req_if ();
wire valid;
wire valid;
wire [63:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -24,6 +25,7 @@ interface VX_alu_req_if ();
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
@@ -43,6 +45,7 @@ interface VX_alu_req_if ();
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,

9
hw/rtl/interfaces/VX_cmt_to_csr_if.sv
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@@ -5,9 +5,12 @@
interface VX_cmt_to_csr_if ();
wire valid;
wire [$clog2(`NUM_THREADS+1)-1:0] commit_size;
wire valid;
`ifdef EXT_F_ENABLE
wire [$clog2(6*`NUM_THREADS+1)-1:0] commit_size;
`else
wire [$clog2(5*`NUM_THREADS+1)-1:0] commit_size;
`endif
modport master (
output valid,
output commit_size

3
hw/rtl/interfaces/VX_commit_if.sv
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@@ -6,6 +6,7 @@
interface VX_commit_if ();
wire valid;
wire [63:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -17,6 +18,7 @@ interface VX_commit_if ();
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
@@ -29,6 +31,7 @@ interface VX_commit_if ();
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,

3
hw/rtl/interfaces/VX_csr_req_if.sv
View File

@@ -6,6 +6,7 @@
interface VX_csr_req_if ();
wire valid;
wire [63:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -20,6 +21,7 @@ interface VX_csr_req_if ();
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
@@ -35,6 +37,7 @@ interface VX_csr_req_if ();
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,

7
hw/rtl/interfaces/VX_decode_if.sv
View File

@@ -6,6 +6,7 @@
interface VX_decode_if ();
wire valid;
wire [63:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -23,7 +24,8 @@ interface VX_decode_if ();
wire ready;
modport master (
output valid,
output valid,
output uuid,
output wid,
output tmask,
output PC,
@@ -42,7 +44,8 @@ interface VX_decode_if ();
);
modport slave (
input valid,
input valid,
input uuid,
input wid,
input tmask,
input PC,

3
hw/rtl/interfaces/VX_fpu_req_if.sv
View File

@@ -6,6 +6,7 @@
interface VX_fpu_req_if ();
wire valid;
wire [63:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -20,6 +21,7 @@ interface VX_fpu_req_if ();
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
@@ -35,6 +37,7 @@ interface VX_fpu_req_if ();
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,

5
hw/rtl/interfaces/VX_gpu_req_if.sv
View File

@@ -6,7 +6,7 @@
interface VX_gpu_req_if();
wire valid;
wire [63:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -19,11 +19,11 @@ interface VX_gpu_req_if();
wire [`NUM_THREADS-1:0][31:0] rs3_data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
@@ -41,6 +41,7 @@ interface VX_gpu_req_if();
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,

3
hw/rtl/interfaces/VX_ibuffer_if.sv
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@@ -6,6 +6,7 @@
interface VX_ibuffer_if ();
wire valid;
wire [63:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -31,6 +32,7 @@ interface VX_ibuffer_if ();
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
@@ -55,6 +57,7 @@ interface VX_ibuffer_if ();
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,

9
hw/rtl/interfaces/VX_ifetch_req_if.sv
View File

@@ -5,14 +5,16 @@
interface VX_ifetch_req_if ();
wire valid;
wire valid;
wire [63:0] uuid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
wire ready;
modport master (
output valid,
output valid,
output uuid,
output tmask,
output wid,
output PC,
@@ -20,7 +22,8 @@ interface VX_ifetch_req_if ();
);
modport slave (
input valid,
input valid,
input uuid,
input tmask,
input wid,
input PC,

7
hw/rtl/interfaces/VX_ifetch_rsp_if.sv
View File

@@ -6,6 +6,7 @@
interface VX_ifetch_rsp_if ();
wire valid;
wire [63:0] uuid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
@@ -13,7 +14,8 @@ interface VX_ifetch_rsp_if ();
wire ready;
modport master (
output valid,
output valid,
output uuid,
output tmask,
output wid,
output PC,
@@ -22,7 +24,8 @@ interface VX_ifetch_rsp_if ();
);
modport slave (
input valid,
input valid,
input uuid,
input tmask,
input wid,
input PC,

3
hw/rtl/interfaces/VX_lsu_req_if.sv
View File

@@ -6,6 +6,7 @@
interface VX_lsu_req_if ();
wire valid;
wire [63:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -21,6 +22,7 @@ interface VX_lsu_req_if ();
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
@@ -37,6 +39,7 @@ interface VX_lsu_req_if ();
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,

6
hw/rtl/interfaces/VX_perf_cache_if.sv
View File

@@ -11,7 +11,7 @@ interface VX_perf_cache_if ();
wire [`PERF_CTR_BITS-1:0] write_misses;
wire [`PERF_CTR_BITS-1:0] bank_stalls;
wire [`PERF_CTR_BITS-1:0] mshr_stalls;
wire [`PERF_CTR_BITS-1:0] pipe_stalls;
wire [`PERF_CTR_BITS-1:0] mem_stalls;
wire [`PERF_CTR_BITS-1:0] crsp_stalls;
modport master (
@@ -21,7 +21,7 @@ interface VX_perf_cache_if ();
output write_misses,
output bank_stalls,
output mshr_stalls,
output pipe_stalls,
output mem_stalls,
output crsp_stalls
);
@@ -32,7 +32,7 @@ interface VX_perf_cache_if ();
input write_misses,
input bank_stalls,
input mshr_stalls,
input pipe_stalls,
input mem_stalls,
input crsp_stalls
);

24
hw/rtl/interfaces/VX_perf_memsys_if.sv
View File

@@ -7,68 +7,50 @@ interface VX_perf_memsys_if ();
wire [`PERF_CTR_BITS-1:0] icache_reads;
wire [`PERF_CTR_BITS-1:0] icache_read_misses;
wire [`PERF_CTR_BITS-1:0] icache_pipe_stalls;
wire [`PERF_CTR_BITS-1:0] icache_crsp_stalls;
wire [`PERF_CTR_BITS-1:0] dcache_reads;
wire [`PERF_CTR_BITS-1:0] dcache_writes;
wire [`PERF_CTR_BITS-1:0] dcache_writes;
wire [`PERF_CTR_BITS-1:0] dcache_read_misses;
wire [`PERF_CTR_BITS-1:0] dcache_write_misses;
wire [`PERF_CTR_BITS-1:0] dcache_bank_stalls;
wire [`PERF_CTR_BITS-1:0] dcache_mshr_stalls;
wire [`PERF_CTR_BITS-1:0] dcache_pipe_stalls;
wire [`PERF_CTR_BITS-1:0] dcache_crsp_stalls;
wire [`PERF_CTR_BITS-1:0] smem_reads;
wire [`PERF_CTR_BITS-1:0] smem_writes;
wire [`PERF_CTR_BITS-1:0] smem_bank_stalls;
wire [`PERF_CTR_BITS-1:0] mem_reads;
wire [`PERF_CTR_BITS-1:0] mem_writes;
wire [`PERF_CTR_BITS-1:0] mem_stalls;
wire [`PERF_CTR_BITS-1:0] mem_latency;
modport master (
output icache_reads,
output icache_read_misses,
output icache_pipe_stalls,
output icache_crsp_stalls,
output dcache_reads,
output dcache_writes,
output dcache_writes,
output dcache_read_misses,
output dcache_write_misses,
output dcache_bank_stalls,
output dcache_mshr_stalls,
output dcache_pipe_stalls,
output dcache_crsp_stalls,
output smem_reads,
output smem_writes,
output smem_bank_stalls,
output mem_reads,
output mem_writes,
output mem_stalls,
output mem_latency
);
modport slave (
input icache_reads,
input icache_read_misses,
input icache_pipe_stalls,
input icache_crsp_stalls,
input dcache_reads,
input dcache_writes,
input dcache_writes,
input dcache_read_misses,
input dcache_write_misses,
input dcache_bank_stalls,
input dcache_mshr_stalls,
input dcache_pipe_stalls,
input dcache_crsp_stalls,
input smem_reads,
input smem_writes,
input smem_bank_stalls,
input mem_reads,
input mem_writes,
input mem_stalls,
input mem_latency
);

32
hw/rtl/interfaces/VX_perf_pipeline_if.sv
View File

@@ -4,18 +4,27 @@
`include "VX_define.vh"
interface VX_perf_pipeline_if ();
wire [`PERF_CTR_BITS-1:0] ibf_stalls;
wire [`PERF_CTR_BITS-1:0] scb_stalls;
wire [`PERF_CTR_BITS-1:0] lsu_stalls;
wire [`PERF_CTR_BITS-1:0] csr_stalls;
wire [`PERF_CTR_BITS-1:0] alu_stalls;
wire [`PERF_CTR_BITS-1:0] loads;
wire [`PERF_CTR_BITS-1:0] stores;
wire [`PERF_CTR_BITS-1:0] branches;
wire [`PERF_CTR_BITS-1:0] ibf_stalls;
wire [`PERF_CTR_BITS-1:0] scb_stalls;
wire [`PERF_CTR_BITS-1:0] lsu_stalls;
wire [`PERF_CTR_BITS-1:0] csr_stalls;
wire [`PERF_CTR_BITS-1:0] alu_stalls;
`ifdef EXT_F_ENABLE
wire [`PERF_CTR_BITS-1:0] fpu_stalls;
wire [`PERF_CTR_BITS-1:0] fpu_stalls;
`endif
wire [`PERF_CTR_BITS-1:0] gpu_stalls;
wire [`PERF_CTR_BITS-1:0] gpu_stalls;
modport master (
modport decode (
output loads,
output stores,
output branches
);
modport issue (
output ibf_stalls,
output scb_stalls,
output lsu_stalls,
@@ -25,9 +34,12 @@ interface VX_perf_pipeline_if ();
output fpu_stalls,
`endif
output gpu_stalls
);
);
modport slave (
input loads,
input stores,
input branches,
input ibf_stalls,
input scb_stalls,
input lsu_stalls,

23
hw/rtl/interfaces/VX_perf_tex_if.sv Normal file
View File

@@ -0,0 +1,23 @@
`ifndef VX_PERF_TEX_IF
`define VX_PERF_TEX_IF
`include "VX_define.vh"
interface VX_perf_tex_if ();
wire [`PERF_CTR_BITS-1:0] mem_reads;
wire [`PERF_CTR_BITS-1:0] mem_latency;
modport master (
output mem_reads,
output mem_latency
);
modport slave (
input mem_reads,
input mem_latency
);
endinterface
`endif

3
hw/rtl/interfaces/VX_tex_req_if.sv
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@@ -6,6 +6,7 @@
interface VX_tex_req_if ();
wire valid;
wire [63:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -20,6 +21,7 @@ interface VX_tex_req_if ();
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
@@ -33,6 +35,7 @@ interface VX_tex_req_if ();
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,

3
hw/rtl/interfaces/VX_tex_rsp_if.sv
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@@ -6,6 +6,7 @@
interface VX_tex_rsp_if ();
wire valid;
wire [63:0] uuid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -16,6 +17,7 @@ interface VX_tex_rsp_if ();
modport master (
output valid,
output uuid,
output wid,
output tmask,
output PC,
@@ -27,6 +29,7 @@ interface VX_tex_rsp_if ();
modport slave (
input valid,
input uuid,
input wid,
input tmask,
input PC,

3
hw/rtl/interfaces/VX_writeback_if.sv
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@@ -6,6 +6,7 @@
interface VX_writeback_if ();
wire valid;
wire [63:0] uuid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
@@ -16,6 +17,7 @@ interface VX_writeback_if ();
modport master (
output valid,
output uuid,
output tmask,
output wid,
output PC,
@@ -27,6 +29,7 @@ interface VX_writeback_if ();
modport slave (
input valid,
input uuid,
input tmask,
input wid,
input PC,