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cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes

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Blaise Tine
2021-11-30 07:08:15 -05:00
parent b995843a5b
commit 41d7e6c63a
79 changed files with 2148 additions and 1372 deletions
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2
hw/rtl/cache/VX_bank.sv vendored
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@@ -48,7 +48,6 @@ module VX_bank #(
output wire perf_read_misses,
output wire perf_write_misses,
output wire perf_mshr_stalls,
output wire perf_pipe_stalls,
`endif
// Core Request
@@ -470,7 +469,6 @@ module VX_bank #(
`ifdef PERF_ENABLE
assign perf_read_misses = do_read_st1 && miss_st1;
assign perf_write_misses = do_write_st1 && miss_st1;
assign perf_pipe_stalls = crsq_stall || mreq_alm_full || mshr_alm_full;
assign perf_mshr_stalls = mshr_alm_full;
`endif