verilator: run all riscv tests

2020-02-13 13:50:57 -05:00
parent e662ef4134
commit 4184980188
3 changed files with 72 additions and 70 deletions
--- a/rtl/simulate/test_bench.h
+++ b/rtl/simulate/test_bench.h
@@ -401,13 +401,13 @@ bool Vortex::simulate(std::string file_to_simulate)

    // std::cout << "Something: " <<  result << '\n';

-    // uint32_t status;
-    // ram.getWord(0, &status);
+    uint32_t status;
+    ram.getWord(0, &status);

    this->print_stats();



-    // return (status == 1);
-    return (1 == 1);
+    return (status == 1);
+    // return (1 == 1);
 }