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minor update

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This commit is contained in:
Blaise Tine
2021-03-22 10:48:26 -04:00
parent a6c489b553
commit 40e3e0105a
2 changed files with 3 additions and 3 deletions
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2
hw/rtl/tex_unit/VX_tex_addr_gen.v → hw/rtl/tex_unit/VX_tex_addr.v
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@@ -1,6 +1,6 @@
`include "VX_tex_define.vh" `include "VX_tex_define.vh"
module VX_tex_addr_gen #( module VX_tex_addr #(
parameter CORE_ID = 0, parameter CORE_ID = 0,
parameter REQ_INFO_WIDTH = 1 parameter REQ_INFO_WIDTH = 1
) ( ) (

4
hw/rtl/tex_unit/VX_tex_unit.v
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@@ -89,9 +89,9 @@ module VX_tex_unit #(
wire [REQ_INFO_WIDTH_M-1:0] mem_rsp_info; wire [REQ_INFO_WIDTH_M-1:0] mem_rsp_info;
wire mem_rsp_ready; wire mem_rsp_ready;
VX_tex_addr_gen #( VX_tex_addr #(
.REQ_INFO_WIDTH (REQ_INFO_WIDTH_A) .REQ_INFO_WIDTH (REQ_INFO_WIDTH_A)
) tex_addr_gen ( ) tex_addr (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),