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fixed afu to cpu mempcy hang

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This commit is contained in:
Blaise Tine
2020-10-28 14:19:13 -07:00
parent 9a9f7955f0
commit 3fe31fc337
7 changed files with 86 additions and 33 deletions
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1
hw/opae/README
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@@ -82,6 +82,7 @@ tar -cvjf vortex.vcd.tar.bz2 build_ase_1c/work/vortex.vcd
tar -zcvf vortex.vcd.tar.gz build_ase_1c/work/vortex.vcd
tar -zcvf run.log.tar.gz build_ase_1c/work/run.log
tar -zcvf vx_scope.vcd.tar.gz vx_scope.vcd
tar -cvjf vx_scope.vcd.tar.bz2 vx_scope.vcd
# decompress VCD trace
tar -zxvf /mnt/c/Users/Blaise/Downloads/vortex.vcd.tar.gz

31
hw/opae/vortex_afu.sv
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@@ -696,7 +696,7 @@ always @(*) begin
af2cp_sTxPort.c0.hdr.mdata = t_ccip_mdata'(cci_rd_req_tag);
end
assign cci_rd_req_fire = af2cp_sTxPort.c0.valid && !cp2af_sRxPort.c0TxAlmFull;
assign cci_rd_req_fire = af2cp_sTxPort.c0.valid;
assign cci_rd_rsp_fire = (STATE_WRITE == state) && cp2af_sRxPort.c0.rspValid;
assign cci_rd_req_tag = CCI_RD_RQ_TAGW'(cci_rd_req_ctr);
@@ -738,7 +738,8 @@ always @(posedge clk) begin
cci_rd_req_enable <= (STATE_WRITE == state)
&& (cci_rd_req_ctr_next < cmd_data_size)
&& (cci_pending_reads_next < CCI_RD_QUEUE_SIZE);
&& (cci_pending_reads_next < CCI_RD_QUEUE_SIZE)
&& !cp2af_sRxPort.c0TxAlmFull;
if (cci_rd_req_fire) begin
cci_rd_req_addr <= cci_rd_req_addr + 1;
@@ -822,7 +823,7 @@ always @(*) begin
af2cp_sTxPort.c1.data = t_ccip_clData'(avs_rdq_dout);
end
assign cci_wr_req_fire = af2cp_sTxPort.c1.valid && !cp2af_sRxPort.c1TxAlmFull;
assign cci_wr_req_fire = af2cp_sTxPort.c1.valid;
assign cci_wr_rsp_fire = (STATE_READ == state) && cp2af_sRxPort.c1.rspValid;
assign cci_pending_writes_next = cci_pending_writes
@@ -852,7 +853,8 @@ begin
end
cci_wr_req_enable <= (STATE_READ == state)
&& (cci_pending_writes_next < CCI_RW_QUEUE_SIZE);
&& (cci_pending_writes_next < CCI_RW_QUEUE_SIZE)
&& !cp2af_sRxPort.c1TxAlmFull;
if (cci_wr_req_fire) begin
assert(cci_wr_req_ctr != 0);
@@ -1074,12 +1076,29 @@ end
`SCOPE_ASSIGN (ccip_sRxPort_c0_hdr_mdata, cp2af_sRxPort.c0.hdr.mdata);
`SCOPE_ASSIGN (ccip_sRxPort_c0_rspValid, cp2af_sRxPort.c0.rspValid);
`SCOPE_ASSIGN (ccip_sRxPort_c1_rspValid, cp2af_sRxPort.c1.rspValid);
`SCOPE_ASSIGN (ccip_sTxPort_c0_fire, af2cp_sTxPort.c0.valid && !cp2af_sRxPort.c0TxAlmFull);
`SCOPE_ASSIGN (ccip_sTxPort_c0_valid, af2cp_sTxPort.c0.valid);
`SCOPE_ASSIGN (ccip_sTxPort_c0_hdr_address, af2cp_sTxPort.c0.hdr.address);
`SCOPE_ASSIGN (ccip_sTxPort_c0_hdr_mdata, af2cp_sTxPort.c0.hdr.mdata);
`SCOPE_ASSIGN (ccip_sTxPort_c1_fire, af2cp_sTxPort.c1.valid && !cp2af_sRxPort.c1TxAlmFull);
`SCOPE_ASSIGN (ccip_sTxPort_c1_valid, af2cp_sTxPort.c1.valid);
`SCOPE_ASSIGN (ccip_sTxPort_c1_hdr_address, af2cp_sTxPort.c1.hdr.address);
`SCOPE_ASSIGN (ccip_sTxPort_c2_mmioRdValid, af2cp_sTxPort.c2.mmioRdValid);
`SCOPE_ASSIGN (ccip_sRxPort_c0TxAlmFull, cp2af_sRxPort.c0TxAlmFull);
`SCOPE_ASSIGN (ccip_sRxPort_c1TxAlmFull, cp2af_sRxPort.c1TxAlmFull);
`SCOPE_ASSIGN (avs_address, avs_address);
`SCOPE_ASSIGN (avs_waitrequest, avs_waitrequest);
`SCOPE_ASSIGN (avs_write_fire, avs_write && !avs_waitrequest);
`SCOPE_ASSIGN (avs_read_fire, avs_read && !avs_waitrequest);
`SCOPE_ASSIGN (avs_byteenable, avs_byteenable);
`SCOPE_ASSIGN (avs_burstcount, avs_burstcount);
`SCOPE_ASSIGN (avs_readdatavalid, avs_readdatavalid);
`SCOPE_ASSIGN (mem_bank_select, mem_bank_select);
`SCOPE_ASSIGN (ccip_dram_rd_req_ctr, cci_dram_rd_req_ctr);
`SCOPE_ASSIGN (ccip_dram_wr_req_ctr, cci_dram_wr_req_ctr);
`SCOPE_ASSIGN (ccip_rd_req_ctr, cci_rd_req_ctr);
`SCOPE_ASSIGN (ccip_rd_rsp_ctr, cci_rd_rsp_ctr);
`SCOPE_ASSIGN (ccip_wr_req_ctr, cci_wr_req_ctr);
`SCOPE_ASSIGN (snp_req_ctr, snp_req_ctr);
`SCOPE_ASSIGN (snp_rsp_ctr, snp_rsp_ctr);
wire scope_changed = `SCOPE_TRIGGER;

2
hw/rtl/VX_platform.vh
View File

@@ -52,7 +52,7 @@
///////////////////////////////////////////////////////////////////////////////
`define USE_FAST_BRAM (* ramstyle="mlab" *)
`define NO_RW_RAM_CHECK (* ramstyle="mlab, no_rw_check" *)
`define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *)
///////////////////////////////////////////////////////////////////////////////

23
hw/scripts/scope.json
View File

@@ -81,12 +81,29 @@
"ccip_sRxPort_c0_hdr_mdata":16,
"?ccip_sRxPort_c0_rspValid":1,
"?ccip_sRxPort_c1_rspValid":1,
"?ccip_sTxPort_c0_fire":1,
"?ccip_sTxPort_c0_valid":1,
"ccip_sTxPort_c0_hdr_address":42,
"ccip_sTxPort_c0_hdr_mdata":16,
"?ccip_sTxPort_c1_fire":1,
"?ccip_sTxPort_c1_valid":1,
"ccip_sTxPort_c1_hdr_address":42,
"ccip_sTxPort_c2_mmioRdValid":1
"ccip_sTxPort_c2_mmioRdValid":1,
"!ccip_sRxPort_c0TxAlmFull":1,
"!ccip_sRxPort_c1TxAlmFull":1,
"avs_address":26,
"!avs_waitrequest":1,
"?avs_write_fire":1,
"?avs_read_fire":1,
"avs_byteenable":64,
"avs_burstcount":4,
"avs_readdatavalid":1,
"mem_bank_select":1,
"ccip_dram_rd_req_ctr":26,
"ccip_dram_wr_req_ctr":26,
"ccip_rd_req_ctr":26,
"ccip_rd_rsp_ctr":3,
"ccip_wr_req_ctr":26,
"snp_req_ctr":"`VX_DRAM_ADDR_WIDTH",
"snp_rsp_ctr":"`VX_DRAM_ADDR_WIDTH"
},
"afu/vortex": {
"!reset": 1,