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minor update

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This commit is contained in:
Blaise Tine
2020-12-24 09:22:44 -08:00
parent 703a861fe9
commit 3fdc49971c
3 changed files with 44 additions and 50 deletions
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6
hw/rtl/VX_databus_arb.v
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@@ -76,7 +76,7 @@ module VX_databus_arb (
wire [1:0] rsp_ready_in; wire [1:0] rsp_ready_in;
wire core_rsp_valid; wire core_rsp_valid;
wire [`NUM_THREADS-1:0] core_rsp_tmask; wire [`NUM_THREADS-1:0] core_rsp_valid_tmask;
assign rsp_data_in[0] = {cache_rsp_if.valid, cache_rsp_if.data, cache_rsp_if.tag}; assign rsp_data_in[0] = {cache_rsp_if.valid, cache_rsp_if.data, cache_rsp_if.tag};
assign rsp_data_in[1] = {smem_rsp_if.valid, smem_rsp_if.data, smem_rsp_if.tag}; assign rsp_data_in[1] = {smem_rsp_if.valid, smem_rsp_if.data, smem_rsp_if.tag};
@@ -95,13 +95,13 @@ module VX_databus_arb (
.data_in (rsp_data_in), .data_in (rsp_data_in),
.ready_in (rsp_ready_in), .ready_in (rsp_ready_in),
.valid_out (core_rsp_valid), .valid_out (core_rsp_valid),
.data_out ({core_rsp_tmask, core_rsp_if.data, core_rsp_if.tag}), .data_out ({core_rsp_valid_tmask, core_rsp_if.data, core_rsp_if.tag}),
.ready_out (core_rsp_if.ready) .ready_out (core_rsp_if.ready)
); );
assign cache_rsp_if.ready = rsp_ready_in[0]; assign cache_rsp_if.ready = rsp_ready_in[0];
assign smem_rsp_if.ready = rsp_ready_in[1]; assign smem_rsp_if.ready = rsp_ready_in[1];
assign core_rsp_if.valid = core_rsp_tmask & {`NUM_THREADS{core_rsp_valid}}; assign core_rsp_if.valid = {`NUM_THREADS{core_rsp_valid}} & core_rsp_valid_tmask;
endmodule endmodule

65
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -38,11 +38,12 @@ module VX_cache_core_rsp_merge #(
reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual;
reg [CORE_TAG_ID_BITS-1:0] sel_tag_id; reg [CORE_TAG_ID_BITS-1:0] sel_tag_id;
reg core_rsp_valid_unaual_any;
wire stall = ~core_rsp_ready && (| core_rsp_valid); wire core_rsp_ready_unqual;
always @(*) begin always @(*) begin
core_rsp_valid_unqual = 0; core_rsp_valid_unqual = 0;
core_rsp_valid_unaual_any = 0;
core_rsp_tag_unqual = 'x; core_rsp_tag_unqual = 'x;
core_rsp_data_unqual = 'x; core_rsp_data_unqual = 'x;
core_rsp_bank_select = 0; core_rsp_bank_select = 0;
@@ -60,33 +61,36 @@ module VX_cache_core_rsp_merge #(
for (integer i = 0; i < NUM_BANKS; i++) begin for (integer i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i] if (per_bank_core_rsp_valid[i]
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == sel_tag_id)) begin && (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == sel_tag_id)) begin
core_rsp_valid_unaual_any = 1;
core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1; core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1;
core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];
core_rsp_bank_select[i] = ~stall; core_rsp_bank_select[i] = core_rsp_ready_unqual;
end end
end end
end end
VX_generic_register #( wire core_rsp_valid_out;
.N(NUM_REQS + (NUM_REQS *`WORD_WIDTH) + CORE_TAG_WIDTH), wire [NUM_REQS-1:0] core_rsp_valid_out_mask;
.R(NUM_REQS)
VX_skid_buffer #(
.DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH))
) pipe_reg ( ) pipe_reg (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.stall (stall), .valid_in (core_rsp_valid_unaual_any),
.flush (1'b0), .data_in ({core_rsp_valid_unqual, core_rsp_tag_unqual, core_rsp_data_unqual}),
.data_in ({core_rsp_valid_unqual, core_rsp_data_unqual, core_rsp_tag_unqual}), .ready_in (core_rsp_ready_unqual),
.data_out ({core_rsp_valid, core_rsp_data, core_rsp_tag}) .valid_out (core_rsp_valid_out),
.data_out ({core_rsp_valid_out_mask, core_rsp_tag, core_rsp_data}),
.ready_out (core_rsp_ready)
); );
for (genvar i = 0; i < NUM_BANKS; i++) begin assign core_rsp_valid = {NUM_REQS{core_rsp_valid_out}} & core_rsp_valid_out_mask;
assign per_bank_core_rsp_ready[i] = core_rsp_bank_select[i];
end
end else begin end else begin
reg [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; reg [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual;
reg [NUM_REQS-1:0] stall; wire [NUM_REQS-1:0] core_rsp_ready_unqual;
always @(*) begin always @(*) begin
core_rsp_valid_unqual = 0; core_rsp_valid_unqual = 0;
@@ -100,31 +104,30 @@ module VX_cache_core_rsp_merge #(
core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1; core_rsp_valid_unqual[per_bank_core_rsp_tid[i]] = 1;
core_rsp_tag_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_tag[i]; core_rsp_tag_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_tag[i];
core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; core_rsp_data_unqual[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];
core_rsp_bank_select[i] = ~stall[per_bank_core_rsp_tid[i]]; core_rsp_bank_select[i] = core_rsp_ready_unqual[per_bank_core_rsp_tid[i]];
end end
end end
end end
for (genvar i = 0; i < NUM_REQS; i++) begin for (genvar i = 0; i < NUM_REQS; i++) begin
assign stall[i] = ~core_rsp_ready[i] && core_rsp_valid[i]; VX_skid_buffer #(
.DATAW (CORE_TAG_WIDTH + `WORD_WIDTH)
VX_generic_register #(
.N(1 + `WORD_WIDTH + CORE_TAG_WIDTH),
.R(1)
) pipe_reg ( ) pipe_reg (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.stall (stall[i]), .valid_in (core_rsp_valid_unqual[i]),
.flush (1'b0), .data_in ({core_rsp_tag_unqual[i], core_rsp_data_unqual[i]}),
.data_in ({core_rsp_valid_unqual[i], core_rsp_data_unqual[i], core_rsp_tag_unqual[i]}), .ready_in (core_rsp_ready_unqual[i]),
.data_out ({core_rsp_valid[i], core_rsp_data[i], core_rsp_tag[i]}) .valid_out (core_rsp_valid[i]),
.data_out ({core_rsp_tag[i],core_rsp_data[i]}),
.ready_out (core_rsp_ready[i])
); );
end end
for (genvar i = 0; i < NUM_BANKS; i++) begin end
assign per_bank_core_rsp_ready[i] = core_rsp_bank_select[i];
end
for (genvar i = 0; i < NUM_BANKS; i++) begin
assign per_bank_core_rsp_ready[i] = core_rsp_bank_select[i];
end end
end else begin end else begin

13
hw/scripts/scope.json
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@@ -60,7 +60,7 @@
"VX_gpu_unit": {}, "VX_gpu_unit": {},
"VX_mem_unit": { "VX_mem_unit": {
"submodules": { "submodules": {
"smem": {"type":"VX_cache", "params":{"NUM_BANKS":"`SNUM_BANKS"}}, "smem": {"type":"VX_cache", "enabled":"`SM_ENABLE", "params":{"NUM_BANKS":"`SNUM_BANKS"}},
"dcache": {"type":"VX_cache", "params":{"NUM_BANKS":"`DNUM_BANKS"}}, "dcache": {"type":"VX_cache", "params":{"NUM_BANKS":"`DNUM_BANKS"}},
"icache": {"type":"VX_cache", "params":{"NUM_BANKS":"`INUM_BANKS"}} "icache": {"type":"VX_cache", "params":{"NUM_BANKS":"`INUM_BANKS"}}
} }
@@ -101,9 +101,7 @@
"ccip_dram_wr_req_ctr":26, "ccip_dram_wr_req_ctr":26,
"ccip_rd_req_ctr":26, "ccip_rd_req_ctr":26,
"ccip_rd_rsp_ctr":3, "ccip_rd_rsp_ctr":3,
"ccip_wr_req_ctr":26, "ccip_wr_req_ctr":26
"snp_req_ctr":"`VX_DRAM_ADDR_WIDTH",
"snp_rsp_ctr":"`VX_DRAM_ADDR_WIDTH"
}, },
"afu/vortex": { "afu/vortex": {
"!reset": 1, "!reset": 1,
@@ -116,12 +114,6 @@
"?dram_rsp_fire": 1, "?dram_rsp_fire": 1,
"dram_rsp_data":"`VX_DRAM_LINE_WIDTH", "dram_rsp_data":"`VX_DRAM_LINE_WIDTH",
"dram_rsp_tag":"`VX_DRAM_TAG_WIDTH", "dram_rsp_tag":"`VX_DRAM_TAG_WIDTH",
"?snp_req_fire": 1,
"snp_req_addr": 32,
"snp_req_inv": 1,
"snp_req_tag":"`VX_SNP_TAG_WIDTH",
"?snp_rsp_fire": 1,
"snp_rsp_tag":"`VX_SNP_TAG_WIDTH",
"busy": 1 "busy": 1
}, },
"afu/vortex/cluster/core/pipeline/fetch/icache_stage": { "afu/vortex/cluster/core/pipeline/fetch/icache_stage": {
@@ -206,7 +198,6 @@
"addr_st2": 32, "addr_st2": 32,
"addr_st3": 32, "addr_st3": 32,
"is_fill_st0": 1, "is_fill_st0": 1,
"is_snp_st0": 1,
"is_mshr_st0": 1, "is_mshr_st0": 1,
"miss_st1": 1, "miss_st1": 1,
"force_miss_st1": 1, "force_miss_st1": 1,