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using shiftreg-based skid buffers

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This commit is contained in:
Blaise Tine
2021-02-28 02:20:09 -08:00
parent e64996946d
commit 3f5fd6d394
10 changed files with 26 additions and 50 deletions
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7
hw/rtl/VX_config.vh
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@@ -8,7 +8,7 @@
`endif `endif
`ifndef NUM_CORES `ifndef NUM_CORES
`define NUM_CORES 4 `define NUM_CORES 1
`endif `endif
`ifndef NUM_WARPS `ifndef NUM_WARPS
@@ -235,11 +235,6 @@
// Pipeline Queues //////////////////////////////////////////////////////////// // Pipeline Queues ////////////////////////////////////////////////////////////
// Size of instruction queue
`ifndef IBUF_SIZE
`define IBUF_SIZE 4
`endif
// Size of LSU Request Queue // Size of LSU Request Queue
`ifndef LSUQ_SIZE `ifndef LSUQ_SIZE
`define LSUQ_SIZE 8 `define LSUQ_SIZE 8

3
hw/rtl/VX_csr_io_arb.v
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@@ -45,8 +45,7 @@ module VX_csr_io_arb (
// responses // responses
wire csr_io_rsp_ready; wire csr_io_rsp_ready;
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (32), .DATAW (32)
.BUFFERED (1)
) csr_io_out_buffer ( ) csr_io_out_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

6
hw/rtl/VX_databus_arb.v
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@@ -39,8 +39,7 @@ module VX_databus_arb (
&& (core_req_if.addr[i][REQ_ADDRW-1:SMEM_ASHIFT-REQ_ASHIFT] < (32-SMEM_ASHIFT)'(`SHARED_MEM_BASE_ADDR >> SMEM_ASHIFT)); && (core_req_if.addr[i][REQ_ADDRW-1:SMEM_ASHIFT-REQ_ASHIFT] < (32-SMEM_ASHIFT)'(`SHARED_MEM_BASE_ADDR >> SMEM_ASHIFT));
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (REQ_DATAW), .DATAW (REQ_DATAW)
.BUFFERED (1)
) cache_out_buffer ( ) cache_out_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -53,8 +52,7 @@ module VX_databus_arb (
); );
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (REQ_DATAW), .DATAW (REQ_DATAW)
.BUFFERED (1)
) smem_out_buffer ( ) smem_out_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

27
hw/rtl/VX_ibuffer.v
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@@ -14,8 +14,8 @@ module VX_ibuffer #(
VX_decode_if ibuf_deq_if VX_decode_if ibuf_deq_if
); );
localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS; localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS;
localparam SIZE = `IBUF_SIZE; localparam SIZE = 3;
localparam ADDRW = $clog2(SIZE+1); localparam ADDRW = $clog2(SIZE);
localparam NWARPSW = $clog2(`NUM_WARPS+1); localparam NWARPSW = $clog2(`NUM_WARPS+1);
reg [`NUM_WARPS-1:0][ADDRW-1:0] used_r; reg [`NUM_WARPS-1:0][ADDRW-1:0] used_r;
@@ -39,22 +39,17 @@ module VX_ibuffer #(
wire push = writing && !is_slot0; wire push = writing && !is_slot0;
wire pop = reading && !alm_empty_r[i]; wire pop = reading && !alm_empty_r[i];
VX_fifo_queue #( VX_skid_buffer #(
.DATAW (DATAW), .DATAW (DATAW)
.SIZE (SIZE),
.BUFFERED (1)
) queue ( ) queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.push (push), .valid_in (push),
.pop (pop), .data_in (q_data_in),
.data_in (q_data_in), .ready_out(pop),
.data_out (q_data_prev[i]), .data_out (q_data_prev[i]),
`UNUSED_PIN (empty), `UNUSED_PIN (ready_in),
`UNUSED_PIN (full), `UNUSED_PIN (valid_out)
`UNUSED_PIN (alm_empty),
`UNUSED_PIN (alm_full),
`UNUSED_PIN (size)
); );
always @(posedge clk) begin always @(posedge clk) begin
@@ -69,7 +64,7 @@ module VX_ibuffer #(
empty_r[i] <= 0; empty_r[i] <= 0;
if (used_r[i] == 1) if (used_r[i] == 1)
alm_empty_r[i] <= 0; alm_empty_r[i] <= 0;
if (used_r[i] == ADDRW'(SIZE)) if (used_r[i] == ADDRW'(SIZE-1))
full_r[i] <= 1; full_r[i] <= 1;
end end
end else if (reading) begin end else if (reading) begin

15
hw/rtl/VX_instr_demux.v
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@@ -38,8 +38,7 @@ module VX_instr_demux (
wire alu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_ALU); wire alu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_ALU);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BITS + `MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)), .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BITS + `MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32))
.BUFFERED (1)
) alu_buffer ( ) alu_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -56,8 +55,7 @@ module VX_instr_demux (
wire lsu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_LSU); wire lsu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_LSU);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)), .DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32))
.BUFFERED (1)
) lsu_buffer ( ) lsu_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -74,8 +72,7 @@ module VX_instr_demux (
wire csr_req_valid = execute_if.valid && (execute_if.ex_type == `EX_CSR); wire csr_req_valid = execute_if.valid && (execute_if.ex_type == `EX_CSR);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32), .DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32)
.BUFFERED (1)
) csr_buffer ( ) csr_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -93,8 +90,7 @@ module VX_instr_demux (
wire fpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_FPU); wire fpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_FPU);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)), .DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32))
.BUFFERED (1)
) fpu_buffer ( ) fpu_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -115,8 +111,7 @@ module VX_instr_demux (
wire gpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_GPU); wire gpu_req_valid = execute_if.valid && (execute_if.ex_type == `EX_GPU);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32)), .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32))
.BUFFERED (1)
) gpu_buffer ( ) gpu_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

3
hw/rtl/cache/VX_bank.v vendored
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@@ -488,8 +488,7 @@ module VX_bank #(
end end
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS), .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS)
.BUFFERED (1)
) core_rsp_req ( ) core_rsp_req (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

6
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -98,8 +98,7 @@ module VX_cache_core_rsp_merge #(
wire core_rsp_valid_any = (| per_bank_core_rsp_valid); wire core_rsp_valid_any = (| per_bank_core_rsp_valid);
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)), .DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH))
.BUFFERED (1)
) pipe_reg ( ) pipe_reg (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -147,8 +146,7 @@ module VX_cache_core_rsp_merge #(
for (genvar i = 0; i < NUM_REQS; i++) begin for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (CORE_TAG_WIDTH + `WORD_WIDTH), .DATAW (CORE_TAG_WIDTH + `WORD_WIDTH)
.BUFFERED (1)
) pipe_reg ( ) pipe_reg (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

3
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -205,8 +205,7 @@ module VX_shared_mem #(
wire crsq_in_valid = ~creq_empty && ~core_rsp_rw; wire crsq_in_valid = ~creq_empty && ~core_rsp_rw;
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH), .DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH)
.BUFFERED (1)
) core_rsp_req ( ) core_rsp_req (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

3
hw/rtl/libs/VX_stream_arbiter.v
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@@ -92,8 +92,7 @@ module VX_stream_arbiter #(
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (DATAW), .DATAW (DATAW),
.PASSTHRU (!BUFFERED), .PASSTHRU (!BUFFERED)
.BUFFERED (1)
) out_buffer ( ) out_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

3
hw/rtl/libs/VX_stream_demux.v
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@@ -40,8 +40,7 @@ module VX_stream_demux #(
for (genvar i = 0; i < NUM_REQS; i++) begin for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #( VX_skid_buffer #(
.DATAW (DATAW), .DATAW (DATAW),
.PASSTHRU (!BUFFERED), .PASSTHRU (!BUFFERED)
.BUFFERED (1)
) out_buffer ( ) out_buffer (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),