using shiftreg-based skid buffers

2021-02-28 02:20:09 -08:00
parent e64996946d
commit 3f5fd6d394
10 changed files with 26 additions and 50 deletions
--- a/hw/rtl/cache/VX_shared_mem.v
+++ b/hw/rtl/cache/VX_shared_mem.v
@@ -205,8 +205,7 @@ module VX_shared_mem #(
    wire crsq_in_valid = ~creq_empty && ~core_rsp_rw;

    VX_skid_buffer #(
-        .DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH), 
-        .BUFFERED (1)
+        .DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH)
    ) core_rsp_req (
        .clk       (clk),
        .reset     (reset),