using shiftreg-based skid buffers

2021-02-28 02:20:09 -08:00
parent e64996946d
commit 3f5fd6d394
10 changed files with 26 additions and 50 deletions
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -488,8 +488,7 @@ module VX_bank #(
    end

    VX_skid_buffer #(
-        .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
-        .BUFFERED (1)
+        .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS)
    ) core_rsp_req (
        .clk       (clk),
        .reset     (reset),