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using shiftreg-based skid buffers

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This commit is contained in:
Blaise Tine
2021-02-28 02:20:09 -08:00
parent e64996946d
commit 3f5fd6d394
10 changed files with 26 additions and 50 deletions
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3
hw/rtl/cache/VX_bank.v vendored
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@@ -488,8 +488,7 @@ module VX_bank #(
end
VX_skid_buffer #(
.DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
.BUFFERED (1)
.DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS)
) core_rsp_req (
.clk (clk),
.reset (reset),

6
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
View File

@@ -98,8 +98,7 @@ module VX_cache_core_rsp_merge #(
wire core_rsp_valid_any = (| per_bank_core_rsp_valid);
VX_skid_buffer #(
.DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)),
.BUFFERED (1)
.DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH))
) pipe_reg (
.clk (clk),
.reset (reset),
@@ -147,8 +146,7 @@ module VX_cache_core_rsp_merge #(
for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #(
.DATAW (CORE_TAG_WIDTH + `WORD_WIDTH),
.BUFFERED (1)
.DATAW (CORE_TAG_WIDTH + `WORD_WIDTH)
) pipe_reg (
.clk (clk),
.reset (reset),

3
hw/rtl/cache/VX_shared_mem.v vendored
View File

@@ -205,8 +205,7 @@ module VX_shared_mem #(
wire crsq_in_valid = ~creq_empty && ~core_rsp_rw;
VX_skid_buffer #(
.DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH),
.BUFFERED (1)
.DATAW (NUM_BANKS * (1 + `WORD_WIDTH) + CORE_TAG_WIDTH)
) core_rsp_req (
.clk (clk),
.reset (reset),