From 3e9abb978b5a9c5705f72c6f8337a0ce3db7c6fd Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 9 Dec 2020 13:03:22 -0800 Subject: [PATCH] fixed typo --- hw/rtl/VX_instr_demux.v | 2 +- hw/rtl/libs/VX_skid_buffer.v | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/rtl/VX_instr_demux.v b/hw/rtl/VX_instr_demux.v index 99409a17..ede08971 100644 --- a/hw/rtl/VX_instr_demux.v +++ b/hw/rtl/VX_instr_demux.v @@ -36,7 +36,7 @@ module VX_instr_demux ( VX_skid_buffer #( .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BR_BITS + 1 + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)), - .REGISTER (1) // ALU has no back pressure, use a simple register + .NOBACKPRESSURE (1) // ALU has no back pressure ) alu_buffer ( .clk (clk), .reset (reset), diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v index 3dc6f2b6..34126bf1 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -1,9 +1,9 @@ `include "VX_platform.vh" module VX_skid_buffer #( - parameter DATAW = 1, - parameter PASSTHRU = 0, - parameter REGISTER = 0 + parameter DATAW = 1, + parameter PASSTHRU = 0, + parameter NOBACKPRESSURE = 0 ) ( input wire clk, input wire reset, @@ -26,7 +26,11 @@ module VX_skid_buffer #( assign data_out = data_in; assign ready_in = ready_out; - end if (REGISTER) begin + end else if (NOBACKPRESSURE) begin + + always @(posedge clk) begin + assert(ready_out) else $error("ready_out should always be asserted"); + end wire stall = valid_out && ~ready_out;