minor update

hw/rtl/VX_lsu_unit.v

@@ -35,7 +35,7 @@ module VX_lsu_unit (
 
     VX_generic_register #(
         .N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65)
-    ) lsu_buffer(
+    ) lsu_buffer (
         .clk  (clk),
         .reset(reset),
         .stall(delay),

hw/rtl/cache/VX_cache_dram_req_arb.v

@@ -42,7 +42,7 @@ module VX_cache_dram_req_arb #(
     parameter PRFQ_SIZE                     = 64,
     parameter PRFQ_STRIDE                   = 2,
 
-// Dram knobs
+    // Dram knobs
     parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
 ) (
     input  wire                                 clk,