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minor update

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This commit is contained in:
Blaise Tine
2020-04-21 22:24:05 -04:00
parent e95af111a5
commit 3e64cb4380
4 changed files with 21 additions and 21 deletions
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22
hw/rtl/VX_dmem_ctrl.v
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@@ -176,19 +176,19 @@ module VX_dmem_ctrl (
.FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE), .FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`DSIMULATED_DRAM_LATENCY_CYCLES) .SIMULATED_DRAM_LATENCY_CYCLES(`DSIMULATED_DRAM_LATENCY_CYCLES)
) gpu_dcache ( ) gpu_dcache (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
// Core req // Core req
.core_req_valid (dcache_req_dcache_if.core_req_valid), .core_req_valid (dcache_req_dcache_if.core_req_valid),
.core_req_read (dcache_req_dcache_if.core_req_read), .core_req_read (dcache_req_dcache_if.core_req_read),
.core_req_write (dcache_req_dcache_if.core_req_write), .core_req_write (dcache_req_dcache_if.core_req_write),
.core_req_addr (dcache_req_dcache_if.core_req_addr), .core_req_addr (dcache_req_dcache_if.core_req_addr),
.core_req_data (dcache_req_dcache_if.core_req_data), .core_req_data (dcache_req_dcache_if.core_req_data),
.core_req_rd (dcache_req_dcache_if.core_req_rd), .core_req_rd (dcache_req_dcache_if.core_req_rd),
.core_req_wb (dcache_req_dcache_if.core_req_wb), .core_req_wb (dcache_req_dcache_if.core_req_wb),
.core_req_warp_num (dcache_req_dcache_if.core_req_warp_num), .core_req_warp_num (dcache_req_dcache_if.core_req_warp_num),
.core_req_pc (dcache_req_dcache_if.core_req_pc), .core_req_pc (dcache_req_dcache_if.core_req_pc),
// Can submit core Req // Can submit core Req
.core_req_ready (dcache_req_dcache_if.core_req_ready), .core_req_ready (dcache_req_dcache_if.core_req_ready),

4
hw/rtl/VX_lsu_unit.v
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@@ -15,7 +15,7 @@ module VX_lsu_unit (
); );
// Generate Addresses // Generate Addresses
wire[`NUM_THREADS-1:0][31:0] address; wire[`NUM_THREADS-1:0][31:0] address;
VX_lsu_addr_gen VX_lsu_addr_gen ( VX_lsu_addr_gen VX_lsu_addr_gen (
.base_address (lsu_req_if.base_address), .base_address (lsu_req_if.base_address),
.offset (lsu_req_if.offset), .offset (lsu_req_if.offset),
.address (address) .address (address)
@@ -35,7 +35,7 @@ module VX_lsu_unit (
VX_generic_register #( VX_generic_register #(
.N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65) .N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65)
) lsu_buffer( ) lsu_buffer (
.clk (clk), .clk (clk),
.reset(reset), .reset(reset),
.stall(delay), .stall(delay),

6
hw/rtl/Vortex.v
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@@ -133,11 +133,11 @@ VX_frE_to_bckE_req_if bckE_req_if(); // New instruction request to EXE/ME
// Back-end to Front-end // Back-end to Front-end
VX_wb_if writeback_if(); // Writeback to GPRs VX_wb_if writeback_if(); // Writeback to GPRs
VX_branch_rsp_if branch_rsp_if(); // Branch Resolution to Fetch VX_branch_rsp_if branch_rsp_if(); // Branch Resolution to Fetch
VX_jal_rsp_if jal_rsp_if(); // Jump resolution to Fetch VX_jal_rsp_if jal_rsp_if(); // Jump resolution to Fetch
// Warp controls // Warp controls
VX_warp_ctl_if warp_ctl_if(); VX_warp_ctl_if warp_ctl_if();
// Cache snooping // Cache snooping
VX_gpu_snp_req_rsp_if gpu_icache_snp_req_if(); VX_gpu_snp_req_rsp_if gpu_icache_snp_req_if();

10
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
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@@ -36,17 +36,17 @@ module VX_cache_dram_req_arb #(
parameter LLVQ_SIZE = 16, parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active} // Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16, parameter FILL_INVALIDAOR_SIZE = 16,
// Prefetcher // Prefetcher
parameter PRFQ_SIZE = 64, parameter PRFQ_SIZE = 64,
parameter PRFQ_STRIDE = 2, parameter PRFQ_STRIDE = 2,
// Dram knobs // Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
// Fill Request // Fill Request
output wire dfqq_full, output wire dfqq_full,
@@ -72,7 +72,7 @@ module VX_cache_dram_req_arb #(
wire pref_valid; wire pref_valid;
wire[31:0] pref_addr; wire[31:0] pref_addr;
wire dwb_valid; wire dwb_valid;
wire dfqq_req; wire dfqq_req;
assign pref_pop = !dwb_valid && !dfqq_req && dram_req_ready && pref_valid; assign pref_pop = !dwb_valid && !dfqq_req && dram_req_ready && pref_valid;