bus arbiters refactoring
This commit is contained in:
Blaise Tine
@@ -1,73 +1,160 @@
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`include "VX_define.vh"
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module VX_smem_arb (
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input wire clk,
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input wire reset,
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module VX_smem_arb #(
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parameter NUM_REQS = 1,
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parameter LANES = 1,
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parameter DATA_SIZE = 1,
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parameter TAG_IN_WIDTH = 1,
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parameter TAG_SEL_IDX = 0,
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parameter BUFFERED_REQ = 0,
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parameter BUFFERED_RSP = 0,
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parameter TYPE = "R",
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localparam ADDR_WIDTH = (32-`CLOG2(DATA_SIZE)),
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localparam DATA_WIDTH = (8 * DATA_SIZE),
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localparam LOG_NUM_REQS = `CLOG2(NUM_REQS),
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localparam TAG_OUT_WIDTH = TAG_IN_WIDTH - LOG_NUM_REQS
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) (
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input wire clk,
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input wire reset,
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// input request
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VX_dcache_req_if core_req_if,
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input wire [LANES-1:0] req_valid_in,
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input wire [LANES-1:0] req_rw_in,
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input wire [LANES-1:0][DATA_SIZE-1:0] req_byteen_in,
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input wire [LANES-1:0][ADDR_WIDTH-1:0] req_addr_in,
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input wire [LANES-1:0][DATA_WIDTH-1:0] req_data_in,
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input wire [LANES-1:0][TAG_IN_WIDTH-1:0] req_tag_in,
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output wire [LANES-1:0] req_ready_in,
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// output requests
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VX_dcache_req_if cache_req_if,
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VX_dcache_req_if smem_req_if,
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// output requests
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output wire [NUM_REQS-1:0][LANES-1:0] req_valid_out,
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output wire [NUM_REQS-1:0][LANES-1:0] req_rw_out,
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output wire [NUM_REQS-1:0][LANES-1:0][DATA_SIZE-1:0] req_byteen_out,
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output wire [NUM_REQS-1:0][LANES-1:0][ADDR_WIDTH-1:0] req_addr_out,
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output wire [NUM_REQS-1:0][LANES-1:0][DATA_WIDTH-1:0] req_data_out,
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output wire [NUM_REQS-1:0][LANES-1:0][TAG_OUT_WIDTH-1:0] req_tag_out,
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input wire [NUM_REQS-1:0][LANES-1:0] req_ready_out,
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// input responses
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VX_dcache_rsp_if cache_rsp_if,
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VX_dcache_rsp_if smem_rsp_if,
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input wire [NUM_REQS-1:0] rsp_valid_in,
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input wire [NUM_REQS-1:0][LANES-1:0] rsp_tmask_in,
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input wire [NUM_REQS-1:0][LANES-1:0][DATA_WIDTH-1:0] rsp_data_in,
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input wire [NUM_REQS-1:0][TAG_OUT_WIDTH-1:0] rsp_tag_in,
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output wire [NUM_REQS-1:0] rsp_ready_in,
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// output response
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VX_dcache_rsp_if core_rsp_if
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);
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localparam REQ_DATAW = `DCORE_ADDR_WIDTH + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + (`DCORE_TAG_WIDTH-1);
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localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
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output wire rsp_valid_out,
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output wire [LANES-1:0] rsp_tmask_out,
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output wire [LANES-1:0][DATA_WIDTH-1:0] rsp_data_out,
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output wire [TAG_IN_WIDTH-1:0] rsp_tag_out,
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input wire rsp_ready_out
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);
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localparam REQ_DATAW = TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH;
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localparam RSP_DATAW = LANES * (1 + DATA_WIDTH) + TAG_IN_WIDTH;
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//
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// handle requests
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//
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if (NUM_REQS > 1) begin
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [LANES-1:0][REQ_DATAW-1:0] req_data_in_merged;
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wire [NUM_REQS-1:0][LANES-1:0][REQ_DATAW-1:0] req_data_out_merged;
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wire [LANES-1:0][LOG_NUM_REQS-1:0] req_sel;
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wire [LANES-1:0][TAG_OUT_WIDTH-1:0] req_tag_in_w;
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for (genvar i = 0; i < LANES; ++i) begin
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assign req_sel[i] = req_tag_in[i][TAG_SEL_IDX +: LOG_NUM_REQS];
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VX_bits_remove #(
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.N (TAG_IN_WIDTH),
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.S (LOG_NUM_REQS),
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.POS (TAG_SEL_IDX)
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) bits_remove (
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.data_in (req_tag_in[i]),
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.data_out (req_tag_in_w[i])
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);
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assign req_data_in_merged[i] = {req_tag_in_w[i], req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]};
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end
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wire [1:0][REQ_DATAW-1:0] req_data_out;
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VX_stream_demux #(
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.NUM_REQS (2),
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.NUM_REQS (NUM_REQS),
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.LANES (LANES),
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.DATAW (REQ_DATAW),
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.BUFFERED (2)
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.BUFFERED (BUFFERED_REQ)
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) req_demux (
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.clk (clk),
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.reset (reset),
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.sel (core_req_if.tag[i][0]),
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.valid_in (core_req_if.valid[i]),
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.data_in ({core_req_if.addr[i], core_req_if.rw[i], core_req_if.byteen[i], core_req_if.data[i], core_req_if.tag[i][`DCORE_TAG_WIDTH-1:1]}),
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.ready_in (core_req_if.ready[i]),
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.valid_out ({smem_req_if.valid[i], cache_req_if.valid[i]}),
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.data_out (req_data_out),
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.ready_out ({smem_req_if.ready[i], cache_req_if.ready[i]})
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);
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.sel_in (req_sel),
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.valid_in (req_valid_in),
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.data_in (req_data_in_merged),
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.ready_in (req_ready_in),
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.valid_out (req_valid_out),
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.data_out (req_data_out_merged),
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.ready_out (req_ready_out)
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);
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for (genvar i = 0; i < NUM_REQS; i++) begin
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for (genvar j = 0; j < LANES; ++j) begin
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assign {req_tag_out[i][j], req_addr_out[i][j], req_rw_out[i][j], req_byteen_out[i][j], req_data_out[i][j]} = req_data_out_merged[i][j];
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end
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end
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///////////////////////////////////////////////////////////////////////
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wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_data_in_merged;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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wire [TAG_IN_WIDTH-1:0] rsp_tag_in_w;
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VX_bits_insert #(
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.N (TAG_OUT_WIDTH),
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.S (LOG_NUM_REQS),
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.POS (TAG_SEL_IDX)
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) bits_insert (
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.data_in (rsp_tag_in[i]),
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.sel_in (LOG_NUM_REQS'(i)),
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.data_out (rsp_tag_in_w)
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);
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assign rsp_data_in_merged[i] = {rsp_tag_in_w, rsp_tmask_in[i], rsp_data_in[i]};
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end
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VX_stream_arbiter #(
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.NUM_REQS (NUM_REQS),
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.LANES (1),
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.DATAW (RSP_DATAW),
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.BUFFERED (BUFFERED_RSP),
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.TYPE (TYPE)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (rsp_valid_in),
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.data_in (rsp_data_in_merged),
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.ready_in (rsp_ready_in),
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.valid_out (rsp_valid_out),
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.data_out ({rsp_tag_out, rsp_tmask_out, rsp_data_out}),
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.ready_out (rsp_ready_out)
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);
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign req_valid_out = req_valid_in;
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assign req_tag_out = req_tag_in;
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assign req_addr_out = req_addr_in;
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assign req_rw_out = req_rw_in;
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assign req_byteen_out = req_byteen_in;
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assign req_data_out = req_data_in;
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assign req_ready_in = req_ready_out;
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assign rsp_valid_out = rsp_valid_in;
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assign rsp_tmask_out = rsp_tmask_in;
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assign rsp_tag_out = rsp_tag_in;
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assign rsp_data_out = rsp_data_in;
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assign rsp_ready_in = rsp_ready_out;
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assign {cache_req_if.addr[i], cache_req_if.rw[i], cache_req_if.byteen[i], cache_req_if.data[i], cache_req_if.tag[i]} = req_data_out[0];
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assign {smem_req_if.addr[i], smem_req_if.rw[i], smem_req_if.byteen[i], smem_req_if.data[i], smem_req_if.tag[i]} = req_data_out[1];
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end
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//
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// handle responses
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//
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VX_stream_arbiter #(
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.NUM_REQS (2),
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.DATAW (RSP_DATAW),
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.TYPE ("X"),
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.BUFFERED (1)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in ({smem_rsp_if.valid, cache_rsp_if.valid}),
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.data_in ({{smem_rsp_if.tmask, smem_rsp_if.data, {smem_rsp_if.tag, 1'b1}},
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{cache_rsp_if.tmask, cache_rsp_if.data, {cache_rsp_if.tag, 1'b0}}}),
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.ready_in ({smem_rsp_if.ready, cache_rsp_if.ready}),
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.valid_out (core_rsp_if.valid),
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.data_out ({core_rsp_if.tmask, core_rsp_if.data, core_rsp_if.tag}),
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.ready_out (core_rsp_if.ready)
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);
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endmodule
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