RTL code refactoring

2020-04-23 12:50:02 -04:00
parent 28d054e295
commit 3cf1a5074b
3 changed files with 10 additions and 13 deletions
--- a/hw/rtl/VX_gpr.v
+++ b/hw/rtl/VX_gpr.v
@@ -15,7 +15,7 @@ module VX_gpr (
    `ifndef ASIC
        assign write_enable = valid_write_request && ((writeback_if.wb != 0)) && (writeback_if.rd != 0);

-        VX_byte_enabled_dual_port_ram be_dp_ram (
+        VX_gpr_ram gpr_ram (
            .we    (write_enable),
            .clk   (clk),
            .reset (reset),
--- a/hw/rtl/libs/VX_byte_enabled_dual_port_ram.v
+++ b/hw/rtl/libs/VX_byte_enabled_dual_port_ram.v
@@ -1,6 +1,6 @@
 `include "VX_define.vh"

-module VX_byte_enabled_dual_port_ram (
+module VX_gpr_ram (
    input wire                          clk,
    input wire                          reset,
 	input wire                          we,