CSRs I/O refactoring
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@@ -7,6 +7,51 @@
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extern "C" {
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#endif
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#ifdef __ASSEMBLY__
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#define __ASM_STR(x) x
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#else
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#define __ASM_STR(x) #x
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#endif
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#define vx_csr_swap(csr, val) ({ \
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unsigned __v = (unsigned )(val); \
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__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1" : "=r" (__v) : "rK" (__v) : "memory"); \
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__v; \
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})
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#define vx_csr_read(csr) ({ \
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register unsigned __v; \
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__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) : "=r" (__v) :: "memory"); \
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__v; \
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})
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#define vx_csr_write(csr, val) ({ \
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unsigned __v = (unsigned )(val); \
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__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" :: "rK" (__v) : "memory"); \
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})
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#define vx_csr_read_set(csr, val) ({ \
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unsigned __v = (unsigned )(val); \
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__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1" : "=r" (__v) : "rK" (__v) : "memory"); \
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__v; \
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})
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#define vx_csr_set(csr, val) ({ \
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unsigned __v = (unsigned )(val); \
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__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" :: "rK" (__v) : "memory"); \
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})
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#define vx_csr_read_clear(csr, val) ({ \
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unsigned __v = (unsigned )(val); \
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__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1" : "=r" (__v) : "rK" (__v) : "memory"); \
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__v; \
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})
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#define vx_csr_clear(csr, val) ({ \
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unsigned __v = (unsigned )(val); \
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__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" :: "rK" (__v) : "memory"); \
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})
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// Set thread mask
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inline void vx_tmc(unsigned num_threads) {
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asm volatile (".insn s 0x6b, 0, x0, 0(%0)" :: "r"(num_threads));
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@@ -95,20 +140,6 @@ inline int vx_num_cores() {
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return result;
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}
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// Return the number of cycles
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inline int vx_num_cycles() {
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int result;
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asm volatile ("csrr %0, %1" : "=r"(result) : "i"(CSR_CYCLE));
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return result;
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}
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// Return the number of instructions
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inline int vx_num_instrs() {
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int result;
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asm volatile ("csrr %0, %1" : "=r"(result) : "i"(CSR_INSTRET));
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return result;
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}
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#define __if(b) vx_split(b); \
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if (b)
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