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CSRs I/O refactoring

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This commit is contained in:
Blaise Tine
2021-06-11 03:08:07 -07:00
parent a46d6cb606
commit 3cc1190cd7
33 changed files with 881 additions and 1385 deletions
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37
hw/rtl/VX_pipeline.v
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@@ -34,19 +34,7 @@ module VX_pipeline #(
input wire icache_rsp_valid,
input wire [31:0] icache_rsp_data,
input wire [`ICORE_TAG_WIDTH-1:0] icache_rsp_tag,
output wire icache_rsp_ready,
// CSR I/O Request
input wire csr_req_valid,
input wire[11:0] csr_req_addr,
input wire csr_req_rw,
input wire[31:0] csr_req_data,
output wire csr_req_ready,
// CSR I/O Response
output wire csr_rsp_valid,
output wire[31:0] csr_rsp_data,
input wire csr_rsp_ready,
output wire icache_rsp_ready,
`ifdef PERF_ENABLE
VX_perf_memsys_if perf_memsys_if,
@@ -116,26 +104,6 @@ module VX_pipeline #(
assign icache_core_rsp_if.tag = icache_rsp_tag;
assign icache_rsp_ready = icache_core_rsp_if.ready;
//
// CSR IO request
//
VX_csr_io_req_if csr_io_req_if();
assign csr_io_req_if.valid = csr_req_valid;
assign csr_io_req_if.rw = csr_req_rw;
assign csr_io_req_if.addr = csr_req_addr;
assign csr_io_req_if.data = csr_req_data;
assign csr_req_ready = csr_io_req_if.ready;
//
// CSR IO response
//
VX_csr_io_rsp_if csr_io_rsp_if();
assign csr_rsp_valid = csr_io_rsp_if.valid;
assign csr_rsp_data = csr_io_rsp_if.data;
assign csr_io_rsp_if.ready = csr_rsp_ready;
///////////////////////////////////////////////////////////////////////////
VX_cmt_to_csr_if cmt_to_csr_if();
@@ -226,9 +194,6 @@ module VX_pipeline #(
.dcache_req_if (dcache_core_req_if),
.dcache_rsp_if (dcache_core_rsp_if),
.csr_io_req_if (csr_io_req_if),
.csr_io_rsp_if (csr_io_rsp_if),
.cmt_to_csr_if (cmt_to_csr_if),