From 3c8620e7702452589718b863a3ec3e820023a5c1 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 21 May 2020 14:51:56 -0400 Subject: [PATCH] minor update --- driver/rtlsim/Makefile | 6 +++--- hw/opae/sources.txt | 14 +++++++++++++- hw/rtl/cache/VX_cache.v | 24 ++++++++++++------------ 3 files changed, 28 insertions(+), 16 deletions(-) diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 5af4660c..cfb62219 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -12,9 +12,9 @@ DBG_PRINT = -DDBG_PRINT_CORE_ICACHE \ -DDBG_PRINT_DRAM \ -DDBG_PRINT_OPAE -#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=2 -#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 +#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 +#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 +MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #DEBUG = 1 diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index fa4ce3e7..467d4ec6 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -3,7 +3,19 @@ vortex_afu.json +define+GLOBAL_BLOCK_SIZE=64 +define+NUM_CORES=2 -+define+L2_ENABLE=0 + ++define+DPRFQ_SIZE=0 ++define+IPRFQ_SIZE=0 ++define+SPRFQ_SIZE=0 ++define+L2PRFQ_SIZE=0 ++define+L3PRFQ_SIZE=0 + ++define+DFILL_INVALIDAOR_SIZE=0 ++define+IFILL_INVALIDAOR_SIZE=0 ++define+SFILL_INVALIDAOR_SIZE=0 ++define+L2FILL_INVALIDAOR_SIZE=0 ++define+L3FILL_INVALIDAOR_SIZE=0 + #+define+DBG_PRINT_CORE_ICACHE #+define+DBG_PRINT_CORE_DCACHE diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index 06f27375..7827905a 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -3,28 +3,28 @@ module VX_cache #( parameter CACHE_ID = 0, // Size of cache in bytes - parameter CACHE_SIZE = 1024, + parameter CACHE_SIZE = 2048, // Size of line inside a bank in bytes parameter BANK_LINE_SIZE = 16, // Number of banks {1, 2, 4, 8,...} parameter NUM_BANKS = 8, // Size of a word in bytes - parameter WORD_SIZE = 16, + parameter WORD_SIZE = 4, // Number of Word requests per cycle {1, 2, 4, 8, ...} - parameter NUM_REQUESTS = 2, + parameter NUM_REQUESTS = 4, // Number of cycles to complete stage 1 (read from memory) - parameter STAGE_1_CYCLES = 2, + parameter STAGE_1_CYCLES = 1, // Queues feeding into banks Knobs {1, 2, 4, 8, ...} // Core Request Queue Size parameter REQQ_SIZE = 8, // Miss Reserv Queue Knob - parameter MRVQ_SIZE = 8, + parameter MRVQ_SIZE = 16, // Dram Fill Rsp Queue Size - parameter DFPQ_SIZE = 2, + parameter DFPQ_SIZE = 16, // Snoop Req Queue Size - parameter SNRQ_SIZE = 8, + parameter SNRQ_SIZE = 16, // Queues for writebacks Knobs {1, 2, 4, 8, ...} // Core Writeback Queue Size @@ -37,7 +37,7 @@ module VX_cache #( parameter LLVQ_SIZE = 16, // Fill Invalidator Size {Fill invalidator must be active} - parameter FILL_INVALIDAOR_SIZE = 16, + parameter FILL_INVALIDAOR_SIZE = 0, // Enable cache writeable parameter WRITE_ENABLE = 1, @@ -49,23 +49,23 @@ module VX_cache #( parameter SNOOP_FORWARDING = 0, // Prefetcher - parameter PRFQ_SIZE = 64, + parameter PRFQ_SIZE = 0, parameter PRFQ_STRIDE = 0, // core request tag size parameter CORE_TAG_WIDTH = 1, // size of tag id in core request tag - parameter CORE_TAG_ID_BITS = 0, + parameter CORE_TAG_ID_BITS = 42, // dram request tag size - parameter DRAM_TAG_WIDTH = 1, + parameter DRAM_TAG_WIDTH = 8, // Number of snoop forwarding requests parameter NUM_SNP_REQUESTS = 2, // Snooping request tag width - parameter SNP_REQ_TAG_WIDTH = 1, + parameter SNP_REQ_TAG_WIDTH = 28, // Snooping forward tag width parameter SNP_FWD_TAG_WIDTH = 1