cache specialization for in-order DRAM reponses

2021-02-13 20:23:29 -08:00
parent 4aaaebab6e
commit 3c37db877a
7 changed files with 84 additions and 64 deletions
--- a/hw/rtl/VX_config.vh
+++ b/hw/rtl/VX_config.vh
@@ -244,7 +244,7 @@

 // Size of LSU Request Queue
 `ifndef LSUQ_SIZE
-`define LSUQ_SIZE (`NUM_WARPS * `NUM_THREADS)
+`define LSUQ_SIZE 8
 `endif

 // Size of FPU Request Queue
@@ -313,7 +313,7 @@

 // Miss Handling Register Size
 `ifndef DMSHR_SIZE
-`define DMSHR_SIZE (`LSUQ_SIZE / 2)
+`define DMSHR_SIZE `LSUQ_SIZE
 `endif

 // DRAM Request Queue Size