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revert byte_enable tag structure

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Blaise Tine
2020-05-23 22:23:25 -04:00
parent c54fa50715
commit 3a9e79d979
5 changed files with 14 additions and 15 deletions
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2
driver/rtlsim/Makefile
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@@ -15,7 +15,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
#DBG_PRINT=$(DBG_PRINT_FLAGS) #DBG_PRINT=$(DBG_PRINT_FLAGS)
#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 #MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
#DEBUG = 1 #DEBUG = 1

1
hw/rtl/cache/VX_cache_config.vh vendored
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@@ -16,7 +16,6 @@
`define BANK_BITS `LOG2UP(NUM_BANKS) `define BANK_BITS `LOG2UP(NUM_BANKS)
`define WORD_WIDTH (8 * WORD_SIZE) `define WORD_WIDTH (8 * WORD_SIZE)
`define BYTE_WIDTH (`WORD_WIDTH / 4)
`define BANK_LINE_WIDTH (8 * BANK_LINE_SIZE) `define BANK_LINE_WIDTH (8 * BANK_LINE_SIZE)

6
hw/rtl/cache/VX_tag_data_access.v vendored
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@@ -65,7 +65,7 @@ module VX_tag_data_access #(
wire use_read_dirty_st1e; wire use_read_dirty_st1e;
wire[`TAG_SELECT_BITS-1:0] use_read_tag_st1e; wire[`TAG_SELECT_BITS-1:0] use_read_tag_st1e;
wire[`BANK_LINE_WIDTH-1:0] use_read_data_st1e; wire[`BANK_LINE_WIDTH-1:0] use_read_data_st1e;
wire[`BANK_LINE_WORDS-1:0][3:0] use_write_enable; wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] use_write_enable;
wire[`BANK_LINE_WIDTH-1:0] use_write_data; wire[`BANK_LINE_WIDTH-1:0] use_write_data;
wire fill_sent; wire fill_sent;
@@ -138,7 +138,7 @@ module VX_tag_data_access #(
wire force_write = real_writefill; wire force_write = real_writefill;
wire should_write; wire should_write;
wire [`BANK_LINE_WORDS-1:0][3:0] we; wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] we;
wire [`BANK_LINE_WIDTH-1:0] data_write; wire [`BANK_LINE_WIDTH-1:0] data_write;
if (WORD_SIZE == BANK_LINE_SIZE) begin if (WORD_SIZE == BANK_LINE_SIZE) begin
@@ -150,7 +150,7 @@ module VX_tag_data_access #(
&& !is_snp_st1e; && !is_snp_st1e;
for (i = 0; i < `BANK_LINE_WORDS; i++) begin for (i = 0; i < `BANK_LINE_WORDS; i++) begin
assign we[i] = (force_write || (should_write && !real_writefill)) ? 4'b1111 : 4'b0000; assign we[i] = (force_write || (should_write && !real_writefill)) ? {WORD_SIZE{1'b1}} : {WORD_SIZE{1'b0}};
end end
assign readword_st1e = use_read_data_st1e; assign readword_st1e = use_read_data_st1e;

18
hw/rtl/cache/VX_tag_data_structure.v vendored
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@@ -21,7 +21,7 @@ module VX_tag_data_structure #(
output wire[`BANK_LINE_WIDTH-1:0] read_data, output wire[`BANK_LINE_WIDTH-1:0] read_data,
input wire invalidate, input wire invalidate,
input wire[`BANK_LINE_WORDS-1:0][3:0] write_enable, input wire[`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] write_enable,
input wire write_fill, input wire write_fill,
input wire[`LINE_SELECT_BITS-1:0] write_addr, input wire[`LINE_SELECT_BITS-1:0] write_addr,
input wire[`TAG_SELECT_BITS-1:0] tag_index, input wire[`TAG_SELECT_BITS-1:0] tag_index,
@@ -29,10 +29,10 @@ module VX_tag_data_structure #(
input wire fill_sent input wire fill_sent
); );
reg [`BANK_LINE_WORDS-1:0][3:0][`BYTE_WIDTH-1:0] data [`BANK_LINE_COUNT-1:0]; reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0]; reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0];
reg valid [`BANK_LINE_COUNT-1:0]; reg valid [`BANK_LINE_COUNT-1:0];
reg dirty [`BANK_LINE_COUNT-1:0]; reg dirty [`BANK_LINE_COUNT-1:0];
assign read_valid = valid [read_addr]; assign read_valid = valid [read_addr];
assign read_dirty = dirty [read_addr]; assign read_dirty = dirty [read_addr];
@@ -66,10 +66,10 @@ module VX_tag_data_structure #(
end end
for (i = 0; i < `BANK_LINE_WORDS; i++) begin for (i = 0; i < `BANK_LINE_WORDS; i++) begin
if (write_enable[i][0]) data[write_addr][i][0] <= write_data[i * `WORD_WIDTH + 0 * `BYTE_WIDTH +: `BYTE_WIDTH]; if (write_enable[i][0]) data[write_addr][i][0] <= write_data[i * `WORD_WIDTH + 0 * 8 +: 8];
if (write_enable[i][1]) data[write_addr][i][1] <= write_data[i * `WORD_WIDTH + 1 * `BYTE_WIDTH +: `BYTE_WIDTH]; if (write_enable[i][1]) data[write_addr][i][1] <= write_data[i * `WORD_WIDTH + 1 * 8 +: 8];
if (write_enable[i][2]) data[write_addr][i][2] <= write_data[i * `WORD_WIDTH + 2 * `BYTE_WIDTH +: `BYTE_WIDTH]; if (write_enable[i][2]) data[write_addr][i][2] <= write_data[i * `WORD_WIDTH + 2 * 8 +: 8];
if (write_enable[i][3]) data[write_addr][i][3] <= write_data[i * `WORD_WIDTH + 3 * `BYTE_WIDTH +: `BYTE_WIDTH]; if (write_enable[i][3]) data[write_addr][i][3] <= write_data[i * `WORD_WIDTH + 3 * 8 +: 8];
end end
end end
end end

2
hw/simulate/simulator.cpp
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@@ -10,7 +10,7 @@ double sc_time_stamp() {
Simulator::Simulator() { Simulator::Simulator() {
// force random values for unitialized signals // force random values for unitialized signals
const char* args[] = {"", "+verilator+rand+reset+1", "+verilator+seed+0"}; const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+50"};
Verilated::commandArgs(3, args); Verilated::commandArgs(3, args);
ram_ = nullptr; ram_ = nullptr;