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Connected cache to bank

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This commit is contained in:
felsabbagh3
2020-03-02 23:24:17 -08:00
parent fc5621cd1d
commit 3a970bbe7b
4 changed files with 132 additions and 97 deletions
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42
rtl/VX_cache/VX_bank.v Normal file
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@@ -0,0 +1,42 @@
`include "VX_cache_config.v"
module VX_bank (
input wire clk,
input wire reset,
// Input Core Request
input wire [`NUMBER_REQUESTS-1:0] bank_valids,
input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr,
input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata,
input wire [4:0] bank_rd,
input wire [1:0] bank_wb,
input wire [`NW_M1:0] bank_warp_num,
input wire [2:0] bank_mem_read,
input wire [2:0] bank_mem_write,
// Output Core WB
input wire bank_wb_pop,
output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] bank_wb_tid,
output wire [4:0] bank_wb_rd,
output wire [1:0] bank_wb_wb,
output wire [`NW_M1:0] bank_wb_warp_num,
output wire [31:0] bank_wb_data,
// Dram Fill Requests
output wire dram_fill_req,
output wire[31:0] dram_fill_req_addr,
input wire dram_fill_req_queue_full,
// Dram Fill Response
input wire dram_fill_rsp,
input wire [31:0] dram_fill_addr,
input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
// Dram WB Requests
input wire dram_wb_queue_pop,
output wire dram_wb_req,
output wire[31:0] dram_wb_req_addr,
output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data
);
endmodule

122
rtl/VX_cache/VX_cache.v
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@@ -41,23 +41,23 @@ module VX_cache (
); );
wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids; wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids;
wire [`NUMBER_BANKS-1:0] per_bank_wb_pop; wire [`NUMBER_BANKS-1:0] per_bank_wb_pop;
wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_wb_tid; wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid;
wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd; wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd;
wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb; wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb;
wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num; wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num;
wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data; wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data;
wire dfqq_full; wire dfqq_full;
wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req; wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req;
wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr; wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop; wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop;
wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req; wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req;
wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr; wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data; wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data;
VX_cache_dram_req_arb VX_cache_dram_req_arb( VX_cache_dram_req_arb VX_cache_dram_req_arb(
.clk (clk), .clk (clk),
@@ -103,34 +103,34 @@ module VX_cache (
generate generate
integer curr_bank; integer curr_bank;
for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin
wire [`NUMBER_REQUESTS-1:0] curr_bank_valids; wire [`NUMBER_REQUESTS-1:0] curr_bank_valids;
wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr; wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr;
wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata; wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata;
wire [4:0] curr_bank_rd; wire [4:0] curr_bank_rd;
wire [1:0] curr_bank_wb; wire [1:0] curr_bank_wb;
wire [`NW_M1:0] curr_bank_warp_num; wire [`NW_M1:0] curr_bank_warp_num;
wire [2:0] curr_bank_mem_read; wire [2:0] curr_bank_mem_read;
wire [2:0] curr_bank_mem_write; wire [2:0] curr_bank_mem_write;
wire curr_bank_wb_pop; wire curr_bank_wb_pop;
wire [`NUMBER_REQUESTS-1:0] curr_bank_wb_tid; wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_wb_tid;
wire [4:0] curr_bank_wb_rd; wire [4:0] curr_bank_wb_rd;
wire [1:0] curr_bank_wb_wb; wire [1:0] curr_bank_wb_wb;
wire [`NW_M1:0] curr_bank_wb_warp_num; wire [`NW_M1:0] curr_bank_wb_warp_num;
wire [31:0] curr_bank_wb_data; wire [31:0] curr_bank_wb_data;
wire curr_bank_dram_fill_rsp; wire curr_bank_dram_fill_rsp;
wire [31:0] curr_bank_dram_fill_rsp_addr; wire [31:0] curr_bank_dram_fill_rsp_addr;
wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data; wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data;
wire curr_bank_dfqq_full; wire curr_bank_dfqq_full;
wire curr_bank_dram_fill_req; wire curr_bank_dram_fill_req;
wire[31:0] curr_bank_dram_fill_req_addr; wire[31:0] curr_bank_dram_fill_req_addr;
wire curr_bank_dram_wb_queue_pop; wire curr_bank_dram_wb_queue_pop;
wire curr_bank_dram_wb_req; wire curr_bank_dram_wb_req;
wire[31:0] curr_bank_dram_wb_req_addr; wire[31:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data; wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data;
// Core Req // Core Req
assign curr_bank_valids = per_bank_valids[curr_bank]; assign curr_bank_valids = per_bank_valids[curr_bank];
@@ -150,16 +150,16 @@ module VX_cache (
assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num; assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num;
assign per_bank_wb_data [curr_bank] = curr_bank_wb_data; assign per_bank_wb_data [curr_bank] = curr_bank_wb_data;
// Dram fill response
assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
// Dram fill request // Dram fill request
assign curr_bank_dfqq_full = dfqq_full; assign curr_bank_dfqq_full = dfqq_full;
assign per_bank_dram_fill_req[curr_bank] = curr_bank_dram_fill_req; assign per_bank_dram_fill_req[curr_bank] = curr_bank_dram_fill_req;
assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr; assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr;
// Dram fill response
assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
// Dram writeback request // Dram writeback request
assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank]; assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank];
assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req; assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req;
@@ -167,8 +167,42 @@ module VX_cache (
assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data; assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data;
VX_cache_bank bank ( VX_bank bank (
.clk (clk),
.reset (reset),
// Core req
.bank_valids (curr_bank_valids),
.bank_addr (curr_bank_addr),
.bank_writedata (curr_bank_writedata),
.bank_rd (curr_bank_rd),
.bank_wb (curr_bank_wb),
.bank_warp_num (curr_bank_warp_num),
.bank_mem_read (curr_bank_mem_read),
.bank_mem_write (curr_bank_mem_write),
// Output core wb
.bank_wb_pop (curr_bank_wb_pop),
.bank_wb_tid (curr_bank_wb_tid),
.bank_wb_rd (curr_bank_wb_rd),
.bank_wb_wb (curr_bank_wb_wb),
.bank_wb_warp_num (curr_bank_wb_warp_num),
.bank_wb_data (curr_bank_wb_data),
// Dram fill req
.dram_fill_req (curr_bank_dram_fill_req),
.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
.dram_fill_req_queue_full(curr_bank_dfqq_full),
// Dram fill rsp
.dram_fill_rsp (curr_bank_dram_fill_rsp),
.dram_fill_addr (curr_bank_dram_fill_rsp_addr),
.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
// Dram writeback
.dram_wb_queue_pop (curr_bank_dram_wb_queue_pop),
.dram_wb_req (curr_bank_dram_wb_req),
.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
.dram_wb_req_data (curr_bank_dram_wb_req_data)
); );
end end

41
rtl/VX_cache/VX_cache_bank.v
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@@ -1,41 +0,0 @@
`include "VX_cache_config.v"
module VX_cache_bank (
input wire clk,
input wire reset,
// Input Core Request
input wire [`NUMBER_REQUESTS-1:0] bank_valids,
input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr,
input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata,
input wire [4:0] bank_rd,
input wire [`NW_M1:0] bank_warp_num,
input wire [2:0] bank_mem_read,
input wire [2:0] bank_mem_write,
// Output Core WB
input wire bank_wb_pop,
output wire [`NUMBER_REQUESTS-1:0] bank_wb_valid,
output wire [4:0] bank_wb_rd,
output wire [1:0] bank_wb_wb,
output wire [`NW_M1:0] bank_wb_warp_num,
output wire [31:0] bank_wb_data,
// Dram Fill Requests
output wire dram_fill_req,
output wire[31:0] dram_fill_req_addr,
input wire dram_fill_req_queue_full,
// Dram Fill Response
input wire dram_fill_rsp,
input wire [31:0] dram_fill_addr,
input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
// Dram WB Requests
input wire dram_wb_queue_pop,
output wire dram_wb_req,
output wire[31:0] dram_wb_req_addr,
output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data
);
endmodule

24
rtl/VX_cache/VX_cache_wb_sel_merge.v
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@@ -4,21 +4,21 @@
module VX_cache_wb_sel_merge ( module VX_cache_wb_sel_merge (
// Per Bank WB // Per Bank WB
input wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_wb_tid, input wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid,
input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd, input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd,
input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb, input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb,
input wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num, input wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num,
input wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data, input wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data,
output wire [`NUMBER_BANKS-1:0] per_bank_wb_pop, output wire [`NUMBER_BANKS-1:0] per_bank_wb_pop,
// Core Writeback // Core Writeback
input wire core_no_wb_slot, input wire core_no_wb_slot,
output reg [`NUMBER_REQUESTS-1:0] core_wb_valid, output reg [`NUMBER_REQUESTS-1:0] core_wb_valid,
output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata
output wire [4:0] core_wb_req_rd, output wire [4:0] core_wb_req_rd,
output wire [1:0] core_wb_req_wb, output wire [1:0] core_wb_req_wb,
output wire [`NW_M1:0] core_wb_warp_num, output wire [`NW_M1:0] core_wb_warp_num,
); );