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Fixed bugs in parameterization

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This commit is contained in:
Savan Roshan
2019-11-06 01:09:30 -05:00
parent fcd3bbc4a1
commit 3a71a2ebdb
5 changed files with 84 additions and 94 deletions
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3
rtl/cache/VX_Cache_Bank.v vendored
View File

@@ -123,6 +123,7 @@ module VX_Cache_Bank
wire lw = (i_p_mem_read == `LW_MEM_READ);
wire lb = (i_p_mem_read == `LB_MEM_READ);
wire lh = (i_p_mem_read == `LH_MEM_READ);
wire lhu = (i_p_mem_read == `LHU_MEM_READ);
@@ -137,7 +138,7 @@ module VX_Cache_Bank
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
wire[31:0] data_unQual = b0 ? (data_use[block_offset] ) :
wire[31:0] data_unQual = (b0 || lw) ? (data_use[block_offset] ) :
b1 ? (data_use[block_offset] >> 8) :
b2 ? (data_use[block_offset] >> 16) :
(data_use[block_offset] >> 24);

4
rtl/cache/VX_cache_bank_valid.v vendored
View File

@@ -16,9 +16,9 @@ module VX_cache_bank_valid
thread_track_banks = 0;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin
thread_track_banks[i_p_addr[t_id][4:2]][t_id] = i_p_valid[t_id];
thread_track_banks[i_p_addr[t_id][2+$clog2(NUMBER_BANKS)-1:2]][t_id] = i_p_valid[t_id];
end
end
endgenerate
endmodule
endmodule