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minor update

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This commit is contained in:
Blaise Tine
2021-07-17 07:22:16 -07:00
parent e0487e4555
commit 382585d33d
3 changed files with 4 additions and 4 deletions
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2
hw/rtl/VX_decode.v
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@@ -40,7 +40,7 @@ module VX_decode #(
reg is_join, is_wstall; reg is_join, is_wstall;
reg [`NUM_REGS-1:0] used_regs; reg [`NUM_REGS-1:0] used_regs;
wire [31:0] instr = ifetch_rsp_if.instr; wire [31:0] instr = ifetch_rsp_if.data;
wire [6:0] opcode = instr[6:0]; wire [6:0] opcode = instr[6:0];
wire [2:0] func3 = instr[14:12]; wire [2:0] func3 = instr[14:12];
wire [6:0] func7 = instr[31:25]; wire [6:0] func7 = instr[31:25];

4
hw/rtl/VX_icache_stage.v
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@@ -62,7 +62,7 @@ module VX_icache_stage #(
assign ifetch_rsp_if.tmask = rsp_tmask; assign ifetch_rsp_if.tmask = rsp_tmask;
assign ifetch_rsp_if.wid = rsp_tag; assign ifetch_rsp_if.wid = rsp_tag;
assign ifetch_rsp_if.PC = rsp_PC; assign ifetch_rsp_if.PC = rsp_PC;
assign ifetch_rsp_if.instr = icache_rsp_if.data; assign ifetch_rsp_if.data = icache_rsp_if.data;
// Can accept new response? // Can accept new response?
assign icache_rsp_if.ready = ifetch_rsp_if.ready; assign icache_rsp_if.ready = ifetch_rsp_if.ready;
@@ -81,7 +81,7 @@ module VX_icache_stage #(
$display("%t: I$%0d req: wid=%0d, PC=%0h", $time, CORE_ID, ifetch_req_if.wid, ifetch_req_if.PC); $display("%t: I$%0d req: wid=%0d, PC=%0h", $time, CORE_ID, ifetch_req_if.wid, ifetch_req_if.PC);
end end
if (icache_rsp_if.valid && icache_rsp_if.ready) begin if (icache_rsp_if.valid && icache_rsp_if.ready) begin
$display("%t: I$%0d rsp: wid=%0d, PC=%0h, instr=%0h", $time, CORE_ID, ifetch_rsp_if.wid, ifetch_rsp_if.PC, ifetch_rsp_if.instr); $display("%t: I$%0d rsp: wid=%0d, PC=%0h, data=%0h", $time, CORE_ID, ifetch_rsp_if.wid, ifetch_rsp_if.PC, ifetch_rsp_if.data);
end end
end end
`endif `endif

2
hw/rtl/interfaces/VX_ifetch_rsp_if.v
View File

@@ -9,7 +9,7 @@ interface VX_ifetch_rsp_if ();
wire [`NUM_THREADS-1:0] tmask; wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid; wire [`NW_BITS-1:0] wid;
wire [31:0] PC; wire [31:0] PC;
wire [31:0] instr; wire [31:0] data;
wire ready; wire ready;
endinterface endinterface