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Generate VCD with ModelSim

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This commit is contained in:
felsabbagh3
2019-10-26 19:35:21 -04:00
parent 6fda88b68f
commit 372c81d90c
2 changed files with 22 additions and 11 deletions
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16
rtl/modelsim/Makefile
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@@ -91,7 +91,17 @@ SRC = \
CMD= \ CMD= \
-do "vcd file vortex.vcd; \ -do "vcd file vortex.vcd; \
run" vcd add -r vortex_tb; \
run; \
quit -f"
OPT=-sv -sv12compat
LIB = vortex_lib
# LOG=-logfile vortex_tb.log
LOG=
# ../shared_memory/VX_set_bit.v \ # ../shared_memory/VX_set_bit.v \
# ../cache/bank.v \ # ../cache/bank.v \
@@ -112,11 +122,11 @@ run"
# vlib # vlib
comp: comp:
vlog -sv -sv12compat -work vortex_lib $(SRC) vlog $(OPT) -work $(LIB) $(SRC)
sim: comp sim: comp
vsim vortex_tb -logfile vortex_tb.log -c -lib vortex_lib $(CMD) vsim vortex_tb $(LOG) -c -lib $(LIB) $(CMD)

17
rtl/modelsim/vortex_tb.v
View File

@@ -28,18 +28,19 @@ module vortex_tb (
integer temp; integer temp;
initial begin initial begin
// $dumpfile("vortex2.vcd");
$dumpvars(0, vortex);
for (temp = 0; temp < 10; temp=temp+1) for (temp = 0; temp < 10; temp=temp+1)
begin begin
icache_response_instruction = 32'h0; if (temp == 0) begin
$display("SIMULATING"); icache_response_instruction = 32'h00000513;
$display("Cycle 1");
end if (temp == 1) begin
$display("Cycle 2",);
icache_response_instruction = 32'h0005006b;
end
end end
// while (!out_ebreak) begin
// icache_response_instruction = 0;
// end
end end
Vortex vortex( Vortex vortex(