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synthesis fixes

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This commit is contained in:
Blaise Tine
2020-03-05 06:58:51 -05:00
parent a86a403ca9
commit 369c2c625c
47 changed files with 633 additions and 2273 deletions
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2
rtl/VX_back_end.v
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@@ -18,7 +18,6 @@ module VX_back_end (
VX_gpu_dcache_res_inter VX_dcache_rsp, VX_gpu_dcache_res_inter VX_dcache_rsp,
VX_gpu_dcache_req_inter VX_dcache_req VX_gpu_dcache_req_inter VX_dcache_req
); );
@@ -31,7 +30,6 @@ assign VX_writeback_inter.wb_warp_num = VX_writeback_temp.wb_warp_num;
// assign VX_writeback_inter(VX_writeback_temp); // assign VX_writeback_inter(VX_writeback_temp);
VX_mw_wb_inter VX_mw_wb(); VX_mw_wb_inter VX_mw_wb();
wire no_slot_mem; wire no_slot_mem;
wire no_slot_exec; wire no_slot_exec;

12
rtl/VX_cache/VX_bank.v
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@@ -176,14 +176,14 @@ module VX_bank (
integer st1_cycle; integer st1_cycle;
always @(*) begin always @(*) begin
assign dfpq_hazard_st0 = 0; dfpq_hazard_st0 = 0;
assign mrvq_hazard_st0 = 0; mrvq_hazard_st0 = 0;
assign reqq_hazard_st0 = 0; reqq_hazard_st0 = 0;
for (st1_cycle = 0; st1_cycle < `STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin for (st1_cycle = 0; st1_cycle < `STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin
if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin
if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign dfpq_hazard_st0 = 1; if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) dfpq_hazard_st0 = 1;
if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign mrvq_hazard_st0 = 1; if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) mrvq_hazard_st0 = 1;
if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) assign reqq_hazard_st0 = 1; if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) reqq_hazard_st0 = 1;
end end
end end
end end

1
rtl/VX_cache/VX_cache.v
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@@ -1,6 +1,5 @@
`include "VX_cache_config.v" `include "VX_cache_config.v"
module VX_cache ( module VX_cache (
input wire clk, input wire clk,
input wire reset, input wire reset,

8
rtl/VX_cache/VX_cache_config.v
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@@ -1,12 +1,10 @@
`ifndef VX_CACHE_CONFIG
`define VX_CACHE_CONFIG
`include "../VX_define.v" `include "../VX_define.v"
`ifndef VX_CACHE_CONFIG
`define VX_CACHE_CONFIG
// ========================================= Configurable Knobs ========================================= // ========================================= Configurable Knobs =========================================
// General Cache Knobs // General Cache Knobs
// Size of cache in bytes // Size of cache in bytes
`define CACHE_SIZE_BYTES 1024 `define CACHE_SIZE_BYTES 1024

5
rtl/VX_cache/VX_cache_core_req_bank_sel.v
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@@ -1,5 +1,4 @@
module VX_cache_core_req_bank_sel ( module VX_cache_core_req_bank_sel (
input wire [`NUMBER_REQUESTS-1:0] core_req_valid, input wire [`NUMBER_REQUESTS-1:0] core_req_valid,
input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr, input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr,
@@ -16,9 +15,9 @@ module VX_cache_core_req_bank_sel (
for (curr_req = 0; curr_req < `NUMBER_REQUESTS; curr_req = curr_req + 1) begin for (curr_req = 0; curr_req < `NUMBER_REQUESTS; curr_req = curr_req + 1) begin
if (`NUMBER_BANKS == 1) begin if (`NUMBER_BANKS == 1) begin
// If there is only one bank, then only map requests to that bank // If there is only one bank, then only map requests to that bank
assign per_bank_valids[0][curr_req] = core_req_valid[curr_req]; per_bank_valids[0][curr_req] = core_req_valid[curr_req];
end else begin end else begin
assign per_bank_valids[core_req_addr[curr_req][`BANK_SELECT_ADDR_RNG]][curr_req] = core_req_valid[curr_req]; per_bank_valids[core_req_addr[curr_req][`BANK_SELECT_ADDR_RNG]][curr_req] = core_req_valid[curr_req];
end end
end end
end end

6
rtl/VX_cache/VX_cache_dram_req_arb.v
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@@ -1,6 +1,5 @@
`include "VX_cache_config.v" `include "VX_cache_config.v"
module VX_cache_dram_req_arb ( module VX_cache_dram_req_arb (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -27,12 +26,13 @@ module VX_cache_dram_req_arb (
); );
wire dfqq_req; wire dfqq_req;
wire[31:0] dfqq_req_addr; wire[31:0] dfqq_req_addr;
wire dfqq_empty; wire dfqq_empty;
wire dwb_valid;
wire dfqq_pop = !dwb_valid && dfqq_req; // If no dwb, and dfqq has valids, then pop wire dfqq_pop = !dwb_valid && dfqq_req; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_fill_req); wire dfqq_push = (|per_bank_dram_fill_req);
VX_cache_dfq_queue VX_cache_dfq_queue( VX_cache_dfq_queue VX_cache_dfq_queue(
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -46,8 +46,6 @@ module VX_cache_dram_req_arb (
.dfqq_full (dfqq_full) .dfqq_full (dfqq_full)
); );
wire dwb_valid;
wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank; wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank;
VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb( VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb(
.valids(per_bank_dram_wb_req), .valids(per_bank_dram_wb_req),

1
rtl/VX_cache/VX_cache_req_queue.v
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@@ -1,4 +1,3 @@
`include "VX_cache_config.v" `include "VX_cache_config.v"
module VX_cache_req_queue ( module VX_cache_req_queue (

15
rtl/VX_cache/VX_cache_wb_sel_merge.v
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@@ -1,6 +1,5 @@
`include "VX_cache_config.v" `include "VX_cache_config.v"
module VX_cache_wb_sel_merge ( module VX_cache_wb_sel_merge (
// Per Bank WB // Per Bank WB
@@ -48,18 +47,18 @@ module VX_cache_wb_sel_merge (
assign core_wb_req_wb = per_bank_wb_wb [main_bank_index]; assign core_wb_req_wb = per_bank_wb_wb [main_bank_index];
assign core_wb_warp_num = per_bank_wb_warp_num[main_bank_index]; assign core_wb_warp_num = per_bank_wb_warp_num[main_bank_index];
genvar this_bank; integer this_bank;
generate generate
always @(*) begin always @(*) begin
assign core_wb_valid = 0; core_wb_valid = 0;
assign core_wb_readdata = 0; core_wb_readdata = 0;
for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin for (this_bank = 0; this_bank < `NUMBER_BANKS; this_bank = this_bank + 1) begin
if (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin if (found_bank && (per_bank_wb_valid[this_bank]) && (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index]) && (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin
assign core_wb_valid[per_bank_wb_tid[this_bank]] = 1; core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
assign core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank]; core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
assign per_bank_wb_pop_unqual[this_bank] = 1; per_bank_wb_pop_unqual[this_bank] = 1;
end else begin end else begin
assign per_bank_wb_pop_unqual[this_bank] = 0; per_bank_wb_pop_unqual[this_bank] = 0;
end end
end end
end end

72
rtl/VX_cache/quartus/Makefile Executable file
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@@ -0,0 +1,72 @@
PROJECT = VX_cache
TOP_LEVEL_ENTITY = VX_cache
SRC_FILE = ../VX_cache.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
QUARTUS_ROOT ?= /tools/reconfig/intel/18.0
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
# Executable Configuration
SYN_ARGS = --parallel --read_settings_files=on
FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
ASM_ARGS =
STA_ARGS = --do_report_timing
# Build targets
all: $(PROJECT).sta.rpt
syn: $(PROJECT).syn.rpt
fit: $(PROJECT).fit.rpt
asm: $(PROJECT).asm.rpt
sta: $(PROJECT).sta.rpt
smart: smart.log
# Target implementations
STAMP = echo done >
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
quartus_syn $(PROJECT) $(SYN_ARGS)
$(STAMP) fit.chg
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
quartus_sta $(PROJECT) $(STA_ARGS)
smart.log: $(PROJECT_FILES)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization
$(PROJECT_FILES):
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../;../../"
syn.chg:
$(STAMP) syn.chg
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg
program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
clean:
rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

1
rtl/VX_cache/quartus/project.sdc Executable file
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@@ -0,0 +1 @@
create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

41
rtl/VX_cache/quartus/project.tcl Normal file
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@@ -0,0 +1,41 @@
load_package flow
package require cmdline
set options { \
{ "project.arg" "" "Project name" } \
{ "family.arg" "" "Device family name" } \
{ "device.arg" "" "Device name" } \
{ "top.arg" "" "Top level module" } \
{ "sdc.arg" "" "Timing Design Constraints file" } \
{ "src.arg" "" "Verilog source file" } \
{ "inc.arg" "." "Include path" } \
}
array set opts [::cmdline::getoptions quartus(args) $options]
project_new $opts(project) -overwrite
set_global_assignment -name FAMILY $opts(family)
set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name VERILOG_FILE $opts(src)
set_global_assignment -name SEARCH_PATH $opts(inc)
set_global_assignment -name SDC_FILE $opts(sdc)
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
proc make_all_pins_virtual {} {
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
export_assignments
}
make_all_pins_virtual
project_close

1
rtl/VX_csr_data.v
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@@ -17,7 +17,6 @@ module VX_csr_data (
); );
// wire[`NT_M1:0][31:0] thread_ids; // wire[`NT_M1:0][31:0] thread_ids;
// wire[`NT_M1:0][31:0] warp_ids; // wire[`NT_M1:0][31:0] warp_ids;

2
rtl/VX_csr_pipe.v
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@@ -8,7 +8,6 @@ module VX_csr_pipe (
VX_wb_inter VX_writeback, VX_wb_inter VX_writeback,
VX_csr_wb_inter VX_csr_wb, VX_csr_wb_inter VX_csr_wb,
output wire stall_gpr_csr output wire stall_gpr_csr
); );
wire[`NT_M1:0] valid_s2; wire[`NT_M1:0] valid_s2;
@@ -96,7 +95,6 @@ module VX_csr_pipe (
csr_vec_read_data_s2; csr_vec_read_data_s2;
assign VX_csr_wb.valid = valid_s2; assign VX_csr_wb.valid = valid_s2;
assign VX_csr_wb.warp_num = warp_num_s2; assign VX_csr_wb.warp_num = warp_num_s2;
assign VX_csr_wb.rd = rd_s2; assign VX_csr_wb.rd = rd_s2;

17
rtl/VX_define.v
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@@ -1,9 +1,7 @@
`ifndef VX_DEFINE
`define VX_DEFINE
`include "./VX_define_synth.v" `include "./VX_define_synth.v"
// `include "./VX_cache/VX_cache_config.v"
// `ifndef VX_DEFINE
// `define VX_DEFINE
`define NT_M1 (`NT-1) `define NT_M1 (`NT-1)
@@ -91,8 +89,6 @@
`define REM 5'd22 `define REM 5'd22
`define REMU 5'd23 `define REMU 5'd23
// WRITEBACK // WRITEBACK
`define WB_ALU 2'h1 `define WB_ALU 2'h1
`define WB_MEM 2'h2 `define WB_MEM 2'h2
@@ -128,7 +124,6 @@
(x <= 1024) ? 10 : \ (x <= 1024) ? 10 : \
-199 -199
// `define PARAM // `define PARAM
// oooooo // oooooo
@@ -244,8 +239,6 @@
`define DCACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`DCACHE_BLOCK-1)) `define DCACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`DCACHE_BLOCK-1))
`define ICACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`ICACHE_BLOCK-1)) `define ICACHE_MEM_REQ_ADDR_MASK (32'hffffffff - (`ICACHE_BLOCK-1))
/////// ///////
//`define SHARED_MEMORY_SIZE 4096 //`define SHARED_MEMORY_SIZE 4096
@@ -271,6 +264,4 @@
`define SHARED_MEMORY_INDEX_OFFSET_ST (`SHARED_MEMORY_BLOCK_OFFSET_ED + 1) `define SHARED_MEMORY_INDEX_OFFSET_ST (`SHARED_MEMORY_BLOCK_OFFSET_ED + 1)
`define SHARED_MEMORY_INDEX_OFFSET_ED (`SHARED_MEMORY_INDEX_OFFSET_ST + $clog2(`SHARED_MEMORY_HEIGHT)-1) `define SHARED_MEMORY_INDEX_OFFSET_ED (`SHARED_MEMORY_INDEX_OFFSET_ST + $clog2(`SHARED_MEMORY_HEIGHT)-1)
`endif
// `endif

8
rtl/VX_define_synth.v
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@@ -1,9 +1,7 @@
`ifndef VX_DEFINE_SYNTH
// `ifndef VX_DEFINE_SYNTH `define VX_DEFINE_SYNTH
// `define VX_DEFINE_SYNTH
`define NT 2 `define NT 2
`define NW 8 `define NW 8
// `endif `endif

7
rtl/VX_dmem_controller.v
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@@ -1,4 +1,3 @@
`include "VX_define.v" `include "VX_define.v"
module VX_dmem_controller ( module VX_dmem_controller (
@@ -16,23 +15,19 @@ module VX_dmem_controller (
VX_gpu_dcache_res_inter VX_dcache_rsp VX_gpu_dcache_res_inter VX_dcache_rsp
); );
wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF; wire to_shm = VX_dcache_req.core_req_addr[0][31:24] == 8'hFF;
wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{~to_shm}}; wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{~to_shm}};
wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}}; wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.core_req_valid & {`NT{to_shm}};
wire[2:0] sm_driver_in_mem_read = !(|sm_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.core_req_mem_read; wire[2:0] sm_driver_in_mem_read = !(|sm_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.core_req_mem_read;
wire[2:0] sm_driver_in_mem_write = !(|sm_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.core_req_mem_write; wire[2:0] sm_driver_in_mem_write = !(|sm_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.core_req_mem_write;
wire[`NT_M1:0][31:0] cache_driver_out_data; wire[`NT_M1:0][31:0] cache_driver_out_data;
wire[`NT_M1:0][31:0] sm_driver_out_data; wire[`NT_M1:0][31:0] sm_driver_out_data;
wire[`NT_M1:0] cache_driver_out_valid; // Not used for now wire[`NT_M1:0] cache_driver_out_valid; // Not used for now
wire sm_delay; wire sm_delay;
// I_Cache Signals // I_Cache Signals
wire[31:0] icache_instruction_out; wire[31:0] icache_instruction_out;
@@ -169,7 +164,7 @@ module VX_dmem_controller (
// ); // );
VX_d_cache#( VX_d_cache #(
.CACHE_SIZE (`ICACHE_SIZE), .CACHE_SIZE (`ICACHE_SIZE),
.CACHE_WAYS (`ICACHE_WAYS), .CACHE_WAYS (`ICACHE_WAYS),
.CACHE_BLOCK (`ICACHE_BLOCK), .CACHE_BLOCK (`ICACHE_BLOCK),

2
rtl/VX_execute_unit.v
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@@ -18,8 +18,6 @@ module VX_execute_unit (
output wire out_delay output wire out_delay
); );
wire[`NT_M1:0][31:0] in_a_reg_data; wire[`NT_M1:0][31:0] in_a_reg_data;
wire[`NT_M1:0][31:0] in_b_reg_data; wire[`NT_M1:0][31:0] in_b_reg_data;
wire[4:0] in_alu_op; wire[4:0] in_alu_op;

1
rtl/VX_fetch.v
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@@ -1,4 +1,3 @@
`include "VX_define.v" `include "VX_define.v"
module VX_fetch ( module VX_fetch (

5
rtl/VX_generic_priority_encoder.v
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@@ -1,3 +1,6 @@
`ifndef VX_GENERIC_PRIORITY_ENCODER
`define VX_GENERIC_PRIORITY_ENCODER
`include "VX_define.v" `include "VX_define.v"
module VX_generic_priority_encoder module VX_generic_priority_encoder
@@ -25,3 +28,5 @@ module VX_generic_priority_encoder
end end
end end
endmodule endmodule
`endif

4
rtl/VX_generic_queue.v
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@@ -1,5 +1,4 @@
module VX_generic_queue module VX_generic_queue
#( #(
parameter DATAW = 4, parameter DATAW = 4,
@@ -17,7 +16,6 @@ module VX_generic_queue
output wire full output wire full
); );
reg[DATAW-1:0] data[SIZE-1:0]; reg[DATAW-1:0] data[SIZE-1:0];
reg[$clog2(SIZE)-1:0] head; reg[$clog2(SIZE)-1:0] head;
reg[$clog2(SIZE)-1:0] tail; reg[$clog2(SIZE)-1:0] tail;
@@ -31,7 +29,7 @@ module VX_generic_queue
head <= 0; head <= 0;
tail <= 0; tail <= 0;
for (i = 0; i < SIZE; i=i+1) begin for (i = 0; i < SIZE; i=i+1) begin
data[i] <= {DATAW{1'0}}; data[i] <= 0;
end end
end else begin end else begin
if (push && !full) begin if (push && !full) begin

4
rtl/VX_generic_register.v
View File

@@ -10,11 +10,8 @@ module VX_generic_register
output wire[(N-1):0] out output wire[(N-1):0] out
); );
reg[(N-1):0] value; reg[(N-1):0] value;
always @(posedge clk or posedge reset) begin always @(posedge clk or posedge reset) begin
if (reset) begin if (reset) begin
value <= 0; value <= 0;
@@ -25,7 +22,6 @@ module VX_generic_register
end end
end end
assign out = value; assign out = value;
endmodule endmodule

1
rtl/VX_generic_stack.v
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@@ -1,3 +1,4 @@
module VX_generic_stack module VX_generic_stack
#( #(
parameter WIDTH = 40, parameter WIDTH = 40,

1
rtl/VX_gpr_stage.v
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@@ -1,4 +1,3 @@
`include "VX_define.v" `include "VX_define.v"
module VX_gpr_stage ( module VX_gpr_stage (

12
rtl/VX_lsu.v
View File

@@ -1,7 +1,5 @@
`include "VX_define.v" `include "VX_define.v"
module VX_lsu ( module VX_lsu (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -16,9 +14,6 @@ module VX_lsu (
output wire out_delay output wire out_delay
); );
// Generate Addresses // Generate Addresses
wire[`NT_M1:0][31:0] address; wire[`NT_M1:0][31:0] address;
VX_lsu_addr_gen VX_lsu_addr_gen VX_lsu_addr_gen VX_lsu_addr_gen
@@ -28,7 +23,6 @@ module VX_lsu (
.address (address) .address (address)
); );
wire[`NT_M1:0][31:0] use_address; wire[`NT_M1:0][31:0] use_address;
wire[`NT_M1:0][31:0] use_store_data; wire[`NT_M1:0][31:0] use_store_data;
wire[`NT_M1:0] use_valid; wire[`NT_M1:0] use_valid;
@@ -39,8 +33,6 @@ module VX_lsu (
wire[1:0] use_wb; wire[1:0] use_wb;
wire[31:0] use_pc; wire[31:0] use_pc;
wire zero = 0; wire zero = 0;
VX_generic_register #(.N(45 + `NW_M1 + 1 + `NT*65)) lsu_buffer( VX_generic_register #(.N(45 + `NW_M1 + 1 + `NT*65)) lsu_buffer(
@@ -66,8 +58,6 @@ module VX_lsu (
// Cache can't accept request // Cache can't accept request
assign out_delay = VX_dcache_rsp.delay_req; assign out_delay = VX_dcache_rsp.delay_req;
// Core Response // Core Response
assign VX_mem_wb.rd = VX_dcache_rsp.core_wb_req_rd; assign VX_mem_wb.rd = VX_dcache_rsp.core_wb_req_rd;
assign VX_mem_wb.wb = VX_dcache_rsp.core_wb_req_wb; assign VX_mem_wb.wb = VX_dcache_rsp.core_wb_req_wb;
@@ -79,8 +69,6 @@ module VX_lsu (
// Core can't accept response // Core can't accept response
assign VX_dcache_req.core_no_wb_slot = no_slot_mem; assign VX_dcache_req.core_no_wb_slot = no_slot_mem;
// integer curr_t; // integer curr_t;
// always @(negedge clk) begin // always @(negedge clk) begin
// for (int curr_t = 0; curr_t < `NT; curr_t=curr_t+1) // for (int curr_t = 0; curr_t < `NT; curr_t=curr_t+1)

2
rtl/VX_scheduler.v
View File

@@ -1,5 +1,3 @@
`include "VX_define.v" `include "VX_define.v"
module VX_scheduler ( module VX_scheduler (

4
rtl/VX_writeback.v
View File

@@ -1,7 +1,5 @@
`include "VX_define.v" `include "VX_define.v"
module VX_writeback ( module VX_writeback (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -17,7 +15,7 @@ module VX_writeback (
output wire no_slot_mem, output wire no_slot_mem,
output wire no_slot_exec, output wire no_slot_exec,
output wire no_slot_csr output wire no_slot_csr
); );
VX_wb_inter VX_writeback_tempp(); VX_wb_inter VX_writeback_tempp();

80
rtl/Vortex.v
View File

@@ -1,6 +1,5 @@
`include "VX_define.v"
// `include "VX_define.v" `include "VX_cache_config.v"
`include "./VX_cache/VX_cache_config.v"
module Vortex module Vortex
/*#( /*#(
@@ -49,60 +48,56 @@ module Vortex
); );
reg[31:0] icache_banks = `ICACHE_BANKS; reg[31:0] icache_banks = `ICACHE_BANKS;
reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK; reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK;
reg[31:0] number_threads = `NT; reg[31:0] number_threads = `NT;
reg[31:0] number_warps = `NW; reg[31:0] number_warps = `NW;
always @(posedge clk) begin always @(posedge clk) begin
icache_banks <= icache_banks; icache_banks <= icache_banks;
icache_num_words_per_block <= icache_num_words_per_block; icache_num_words_per_block <= icache_num_words_per_block;
number_threads <= number_threads; number_threads <= number_threads;
number_warps <= number_warps; number_warps <= number_warps;
end end
wire memory_delay; wire memory_delay;
wire exec_delay; wire exec_delay;
wire gpr_stage_delay; wire gpr_stage_delay;
wire schedule_delay; wire schedule_delay;
// Dcache Interface // Dcache Interface
VX_gpu_dcache_res_inter VX_dcache_rsp(); VX_gpu_dcache_res_inter VX_dcache_rsp();
VX_gpu_dcache_req_inter VX_dcache_req(); VX_gpu_dcache_req_inter VX_dcache_req();
VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req(); VX_gpu_dcache_dram_req_inter VX_gpu_dcache_dram_req();
VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res(); VX_gpu_dcache_dram_res_inter VX_gpu_dcache_dram_res();
assign VX_gpu_dcache_dram_res.dram_fill_rsp = dram_fill_rsp; assign VX_gpu_dcache_dram_res.dram_fill_rsp = dram_fill_rsp;
assign VX_gpu_dcache_dram_res.dram_fill_rsp_addr = dram_fill_rsp_addr; assign VX_gpu_dcache_dram_res.dram_fill_rsp_addr = dram_fill_rsp_addr;
assign dram_req = VX_gpu_dcache_dram_req.dram_req; assign dram_req = VX_gpu_dcache_dram_req.dram_req;
assign dram_req_write = VX_gpu_dcache_dram_req.dram_req_write; assign dram_req_write = VX_gpu_dcache_dram_req.dram_req_write;
assign dram_req_read = VX_gpu_dcache_dram_req.dram_req_read; assign dram_req_read = VX_gpu_dcache_dram_req.dram_req_read;
assign dram_req_addr = VX_gpu_dcache_dram_req.dram_req_addr; assign dram_req_addr = VX_gpu_dcache_dram_req.dram_req_addr;
assign dram_req_size = VX_gpu_dcache_dram_req.dram_req_size; assign dram_req_size = VX_gpu_dcache_dram_req.dram_req_size;
assign dram_expected_lat = `SIMULATED_DRAM_LATENCY_CYCLES; assign dram_expected_lat = `SIMULATED_DRAM_LATENCY_CYCLES;
assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept; assign dram_fill_accept = VX_gpu_dcache_dram_req.dram_fill_accept;
genvar wordy; genvar wordy;
generate generate
for (wordy = 0; wordy < `BANK_LINE_SIZE_WORDS; wordy=wordy+1) begin for (wordy = 0; wordy < `BANK_LINE_SIZE_WORDS; wordy=wordy+1) begin
assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[wordy] = dram_fill_rsp_data[wordy]; assign VX_gpu_dcache_dram_res.dram_fill_rsp_data[wordy] = dram_fill_rsp_data[wordy];
assign dram_req_data[wordy] = VX_gpu_dcache_dram_req.dram_req_data[wordy]; assign dram_req_data[wordy] = VX_gpu_dcache_dram_req.dram_req_data[wordy];
end end
endgenerate endgenerate
wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000);
wire[31:0] temp_io_data = VX_dcache_req.core_req_valid[0];
assign io_valid = temp_io_valid;
assign io_data = temp_io_data;
wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.core_req_valid) && (VX_dcache_req.core_req_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.core_req_addr[0] == 32'h00010000);
wire[31:0] temp_io_data = VX_dcache_req.core_req_valid[0];
assign io_valid = temp_io_valid;
assign io_data = temp_io_data;
VX_icache_response_inter icache_response_fe(); VX_icache_response_inter icache_response_fe();
@@ -114,8 +109,6 @@ assign io_data = temp_io_data;
//assign icache_response_fe.instruction = icache_response_instruction; //assign icache_response_fe.instruction = icache_response_instruction;
assign icache_request_pc_address = icache_request_fe.pc_address; assign icache_request_pc_address = icache_request_fe.pc_address;
assign o_m_valid_i = VX_dram_req_rsp_icache.o_m_valid; assign o_m_valid_i = VX_dram_req_rsp_icache.o_m_valid;
assign o_m_read_addr_i = VX_dram_req_rsp_icache.o_m_read_addr; assign o_m_read_addr_i = VX_dram_req_rsp_icache.o_m_read_addr;
assign o_m_evict_addr_i = VX_dram_req_rsp_icache.o_m_evict_addr; assign o_m_evict_addr_i = VX_dram_req_rsp_icache.o_m_evict_addr;
@@ -132,11 +125,8 @@ for (curr_bank = 0; curr_bank < `ICACHE_BANKS; curr_bank = curr_bank + 1) begin
end end
end end
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// Front-end to Back-end // Front-end to Back-end
VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM
@@ -204,6 +194,7 @@ VX_dmem_controller VX_dmem_controller(
.VX_dcache_req (VX_dcache_req), .VX_dcache_req (VX_dcache_req),
.VX_dcache_rsp (VX_dcache_rsp) .VX_dcache_rsp (VX_dcache_rsp)
); );
// VX_csr_handler vx_csr_handler( // VX_csr_handler vx_csr_handler(
// .clk (clk), // .clk (clk),
// .in_decode_csr_address(decode_csr_address), // .in_decode_csr_address(decode_csr_address),
@@ -213,9 +204,6 @@ VX_dmem_controller VX_dmem_controller(
// .out_decode_csr_data (csr_decode_csr_data) // .out_decode_csr_data (csr_decode_csr_data)
// ); // );
endmodule // Vortex endmodule // Vortex

1
rtl/byte_enabled_simple_dual_port_ram.v
View File

@@ -1,7 +1,6 @@
`include "VX_define.v" `include "VX_define.v"
module byte_enabled_simple_dual_port_ram module byte_enabled_simple_dual_port_ram
( (
input we, clk, input we, clk,

2
rtl/cache/VX_Cache_Bank.v vendored
View File

@@ -3,8 +3,6 @@
// Also make sure all possible output states are transmitted back to the bank correctly // Also make sure all possible output states are transmitted back to the bank correctly
`include "VX_define.v" `include "VX_define.v"
// `include "VX_cache_data.v"
module VX_Cache_Bank module VX_Cache_Bank
#( #(

2
rtl/cache/VX_cache_data.v vendored
View File

@@ -1,5 +1,3 @@
`include "VX_define.v" `include "VX_define.v"
module VX_cache_data module VX_cache_data

2
rtl/cache/VX_cache_data_per_index.v vendored
View File

@@ -1,5 +1,3 @@
`include "VX_define.v" `include "VX_define.v"
module VX_cache_data_per_index module VX_cache_data_per_index

5
rtl/cache/VX_d_cache.v vendored
View File

@@ -9,9 +9,10 @@
// - Send in a response from memory of what the data is from the test bench // - Send in a response from memory of what the data is from the test bench
`include "VX_define.v" `include "VX_define.v"
//`include "VX_Cache_Bank.v"
//`include "VX_cache_bank_valid.v"
//`include "VX_priority_encoder.v" //`include "VX_priority_encoder.v"
// `include "VX_Cache_Bank.v" //`include "VX_priority_encoder_w_mask.v"
//`include "cache_set.v"
module VX_d_cache module VX_d_cache
#( #(

1
rtl/cache/VX_d_cache_encapsulate.v vendored
View File

@@ -1,4 +1,3 @@
`include "VX_define.v" `include "VX_define.v"
`define NUM_WORDS_PER_BLOCK 4 `define NUM_WORDS_PER_BLOCK 4

70
rtl/cache/quartus/Makefile vendored Executable file
View File

@@ -0,0 +1,70 @@
PROJECT = VX_d_cache
TOP_LEVEL_ENTITY = VX_d_cache
SRC_FILE = ../VX_d_cache.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
# Executable Configuration
SYN_ARGS = --parallel --read_settings_files=on
FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
ASM_ARGS =
STA_ARGS = --do_report_timing
# Build targets
all: $(PROJECT).sta.rpt
syn: $(PROJECT).syn.rpt
fit: $(PROJECT).fit.rpt
asm: $(PROJECT).asm.rpt
sta: $(PROJECT).sta.rpt
smart: smart.log
# Target implementations
STAMP = echo done >
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
quartus_syn $(PROJECT) $(SYN_ARGS)
$(STAMP) fit.chg
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
quartus_sta $(PROJECT) $(STA_ARGS)
smart.log: $(PROJECT_FILES)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization
$(PROJECT_FILES):
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../;../../"
syn.chg:
$(STAMP) syn.chg
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg
program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
clean:
rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

1
rtl/cache/quartus/project.sdc vendored Executable file
View File

@@ -0,0 +1 @@
create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

41
rtl/cache/quartus/project.tcl vendored Normal file
View File

@@ -0,0 +1,41 @@
load_package flow
package require cmdline
set options { \
{ "project.arg" "" "Project name" } \
{ "family.arg" "" "Device family name" } \
{ "device.arg" "" "Device name" } \
{ "top.arg" "" "Top level module" } \
{ "sdc.arg" "" "Timing Design Constraints file" } \
{ "src.arg" "" "Verilog source file" } \
{ "inc.arg" "." "Include path" } \
}
array set opts [::cmdline::getoptions quartus(args) $options]
project_new $opts(project) -overwrite
set_global_assignment -name FAMILY $opts(family)
set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name VERILOG_FILE $opts(src)
set_global_assignment -name SEARCH_PATH $opts(inc)
set_global_assignment -name SDC_FILE $opts(sdc)
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
proc make_all_pins_virtual {} {
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
export_assignments
}
make_all_pins_virtual
project_close

2
rtl/pipe_regs/VX_d_e_reg.v
View File

@@ -1,5 +1,3 @@
`include "../VX_define.v" `include "../VX_define.v"
module VX_d_e_reg ( module VX_d_e_reg (

41
rtl/quartus/Makefile
View File

@@ -1,60 +1,57 @@
PROJECT = Vortex PROJECT = Vortex
TOP_LEVEL_ENTITY = Vortex TOP_LEVEL_ENTITY = Vortex
SRC_FILE = Vortex.v SRC_FILE = ../Vortex.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
QUARTUS_ROOT ?= /tools/reconfig/intel/18.0 QUARTUS_ROOT ?= /tools/reconfig/intel/18.0
# Part, Family # Part, Family
FAMILY = "Arria 10" FAMILY = "Arria 10"
DEVICE = 10AX115N4F45I3SG DEVICE = 10AX115N3F40E2SG
# Executable Configuration # Executable Configuration
SYN_ARGS = --read_settings_files=on SYN_ARGS = --parallel --read_settings_files=on
FIT_ARGS = --part=$(DEVICE) --read_settings_files=on FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
ASM_ARGS = ASM_ARGS =
STA_ARGS = --do_report_timing STA_ARGS = --do_report_timing
# Build targets # Build targets
all: smart.log $(PROJECT).asm.rpt $(PROJECT).sta.rpt all: $(PROJECT).sta.rpt
syn: smart.log $(PROJECT).syn.rpt syn: $(PROJECT).syn.rpt
fit: smart.log $(PROJECT).fit.rpt fit: $(PROJECT).fit.rpt
asm: smart.log $(PROJECT).asm.rpt asm: $(PROJECT).asm.rpt
sta: smart.log $(PROJECT).sta.rpt sta: $(PROJECT).sta.rpt
smart: smart.log smart: smart.log
# Target implementations # Target implementations
STAMP = echo done > STAMP = echo done >
$(PROJECT).syn.rpt: syn.chg $(SOURCE_FILES) $(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t make_pins_virtual.tcl quartus_syn $(PROJECT) $(SYN_ARGS)
$(QUARTUS_ROOT)/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS)
# $(QUARTUS_ROOT)/quartus/bin/quartus_sh -t make_pins_virtual.tcl
$(STAMP) fit.chg $(STAMP) fit.chg
$(PROJECT).fit.rpt: fit.chg $(PROJECT).syn.rpt $(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
$(QUARTUS_ROOT)/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS) quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg $(STAMP) asm.chg
$(STAMP) sta.chg $(STAMP) sta.chg
$(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt $(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
$(QUARTUS_ROOT)/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS) quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt $(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
$(QUARTUS_ROOT)/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS) quartus_sta $(PROJECT) $(STA_ARGS)
$(QUARTUS_ROOT)/quartus/bin/quartus_sta -t VX_timing.tcl
smart.log: $(PROJECT_FILES) smart.log: $(PROJECT_FILES)
$(QUARTUS_ROOT)/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization # Project initialization
$(PROJECT_FILES): $(PROJECT_FILES):
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../interfaces;../pipe_regs;../cache;../VX_cache;../shared_memory;../compat"
syn.chg: syn.chg:
$(STAMP) syn.chg $(STAMP) syn.chg
@@ -72,4 +69,4 @@ program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
clean: clean:
rm -rf *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db output_files tmp-clearbox bin/ rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

30
rtl/quartus/VX_gpr_syn.qpf
View File

@@ -1,30 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
# Date created = 00:18:19 September 11, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.0"
DATE = "00:18:19 September 11, 2019"
# Revisions
PROJECT_REVISION = "VX_gpr_syn"

1615
rtl/quartus/VX_gpr_syn.qsf
View File

File diff suppressed because it is too large Load Diff

1
rtl/quartus/asm.chg
View File

@@ -1 +0,0 @@
done

29
rtl/quartus/make_pins_virtual.tcl
View File

@@ -1,29 +0,0 @@
load_package flow
package require cmdline
project_open Vortex
proc make_all_pins_virtual { args } {
remove_all_instance_assignments -name VIRTUAL_PIN
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
if { -1 == [lsearch -exact { clk, reset } $pin_name] } {
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
} else {
post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
}
}
export_assignments
}
make_all_pins_virtual

2
rtl/quartus/map.chg
View File

@@ -1 +1 @@
Wed Sep 11 00:18:22 2019 Thu Mar 05 06:08:03 2020

111
rtl/quartus/project.tcl
View File

@@ -1,3 +1,4 @@
load_package flow
package require cmdline package require cmdline
set options { \ set options { \
@@ -7,6 +8,7 @@ set options { \
{ "top.arg" "" "Top level module" } \ { "top.arg" "" "Top level module" } \
{ "sdc.arg" "" "Timing Design Constraints file" } \ { "sdc.arg" "" "Timing Design Constraints file" } \
{ "src.arg" "" "Verilog source file" } \ { "src.arg" "" "Verilog source file" } \
{ "inc.arg" "." "Include path" } \
} }
array set opts [::cmdline::getoptions quartus(args) $options] array set opts [::cmdline::getoptions quartus(args) $options]
@@ -16,103 +18,24 @@ project_new $opts(project) -overwrite
set_global_assignment -name FAMILY $opts(family) set_global_assignment -name FAMILY $opts(family)
set_global_assignment -name DEVICE $opts(device) set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name VERILOG_FILE $opts(src)
set_global_assignment -name SEARCH_PATH ../ set_global_assignment -name SEARCH_PATH $opts(inc)
set_global_assignment -name SDC_FILE $opts(sdc)
set_global_assignment -name VERILOG_FILE ../VX_define.v
set_global_assignment -name VERILOG_FILE ../cache/cache_set.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dram_req_rsp_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_wstall_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_join_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_data_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_exec_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_req_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpu_inst_req_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_lsu_req_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_exec_unit_req_inter.v
set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v
set_global_assignment -name VERILOG_FILE ../cache/VX_generic_pe.v
set_global_assignment -name VERILOG_FILE ../cache/VX_cache_data_per_index.v
set_global_assignment -name VERILOG_FILE ../cache/VX_cache_data.v
set_global_assignment -name VERILOG_FILE ../cache/VX_cache_bank_valid.v
set_global_assignment -name VERILOG_FILE ../cache/VX_Cache_Bank.v
set_global_assignment -name VERILOG_FILE ../cache/VX_d_cache.v
set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory_block.v
set_global_assignment -name VERILOG_FILE ../shared_memory/VX_shared_memory.v
set_global_assignment -name VERILOG_FILE ../shared_memory/VX_priority_encoder_sm.v
set_global_assignment -name VERILOG_FILE ../shared_memory/VX_bank_valids.v
set_global_assignment -name VERILOG_FILE ../compat/VX_divide.v
set_global_assignment -name VERILOG_FILE ../compat/VX_mult.v
set_global_assignment -name VERILOG_FILE ../VX_alu.v
set_global_assignment -name VERILOG_FILE ../VX_back_end.v
set_global_assignment -name VERILOG_FILE ../VX_context.v
set_global_assignment -name VERILOG_FILE ../VX_context_slave.v
set_global_assignment -name VERILOG_FILE ../VX_decode.v
set_global_assignment -name VERILOG_FILE ../VX_execute.v
set_global_assignment -name VERILOG_FILE ../VX_fetch.v
set_global_assignment -name VERILOG_FILE ../VX_forwarding.v
set_global_assignment -name VERILOG_FILE ../VX_front_end.v
set_global_assignment -name VERILOG_FILE ../VX_generic_register.v
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
set_global_assignment -name VERILOG_FILE ../VX_gpr_stage.v
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v
set_global_assignment -name VERILOG_FILE ../VX_inst_multiplex.v
set_global_assignment -name VERILOG_FILE ../VX_memory.v
set_global_assignment -name VERILOG_FILE ../VX_register_file.v
set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v
set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v
set_global_assignment -name VERILOG_FILE ../VX_warp.v
set_global_assignment -name VERILOG_FILE ../VX_writeback.v
set_global_assignment -name VERILOG_FILE ../VX_csr_wrapper.v
set_global_assignment -name VERILOG_FILE ../VX_gpgpu_inst.v
set_global_assignment -name VERILOG_FILE ../VX_execute_unit.v
set_global_assignment -name VERILOG_FILE ../VX_lsu.v
set_global_assignment -name VERILOG_FILE ../VX_scheduler.v
set_global_assignment -name VERILOG_FILE ../VX_dmem_controller.v
set_global_assignment -name VERILOG_FILE ../Vortex.v
set_global_assignment -name SDC_FILE vortex.sdc
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
proc make_all_pins_virtual {} {
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
export_assignments
}
# set where [file dirname [info script]] make_all_pins_virtual
# source [file join $where make_pins_virtual.tcl]
project_close project_close
# set_global_assignment -name VERILOG_FILE $opts(src)

15
rtl/quartus/smart.log
View File

@@ -1,4 +1,3 @@
Info (292036): Thank you for using the Quartus Prime software 30-day evaluation. You have 0 days remaining (until Sep 11, 2019) to use the Quartus Prime software with compilation and simulation support.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus Prime Shell Info: Running Quartus Prime Shell
Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
@@ -15,13 +14,13 @@ Info: Running Quartus Prime Shell
Info: the sole purpose of programming logic devices manufactured by Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details. Info: refer to the applicable agreement for further details.
Info: Processing started: Wed Sep 11 00:18:22 2019 Info: Processing started: Thu Mar 5 06:08:03 2020
Info: Command: quartus_sh --determine_smart_action VX_gpr_syn Info: Command: quartus_sh --determine_smart_action Vortex
Info: Quartus(args): VX_gpr_syn Info: Quartus(args): Vortex
Info: SMART_ACTION = SOURCE Info: SMART_ACTION = SOURCE
Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 687 megabytes Info: Peak virtual memory: 689 megabytes
Info: Processing ended: Wed Sep 11 00:18:22 2019 Info: Processing ended: Thu Mar 5 06:08:04 2020
Info: Elapsed time: 00:00:00 Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00 Info: Total CPU time (on all processors): 00:00:01

40
rtl/quartus/vortex.ini
View File

@@ -1,40 +0,0 @@
load_package flow
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
set_global_assignment -name SDC_FILE vortex.sdc
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 80
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
# pins configuration
package require cmdline
proc make_all_pins_virtual { args } {
set options {\
{ "exclude.arg" "" "List of signals to exclude" } \
}
array set opts [::cmdline::getoptions quartus(args) $options]
remove_all_instance_assignments -name VIRTUAL_PIN
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
if { -1 == [lsearch -exact $opts(excludes) $pin_name] } {
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
} else {
post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
}
}
export_assignments
}
make_all_pins_virtual -exclude { clk, reset }

2
rtl/quartus/vortex.sdc
View File

@@ -1,6 +1,6 @@
set_time_format -unit ns -decimal_places 3 set_time_format -unit ns -decimal_places 3
create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
derive_pll_clocks -create_base_clocks derive_pll_clocks -create_base_clocks
derive_clock_uncertainty derive_clock_uncertainty