synthesis fixes

rtl/VX_generic_register.v

@@ -10,11 +10,8 @@ module VX_generic_register
 		output wire[(N-1):0] out
 	);
 
-
 	reg[(N-1):0] value;
 
-
-
 	always @(posedge clk or posedge reset) begin
 		if (reset) begin
 			value <= 0;
@@ -25,7 +22,6 @@ module VX_generic_register
 		end
 	end
 
-
 	assign out = value;
 
 endmodule