reset network optimization

This commit is contained in:
Blaise Tine
2021-07-01 18:05:59 -07:00
parent 65c1078158
commit 360f8e4e37
6 changed files with 74 additions and 71 deletions

View File

@@ -33,17 +33,17 @@ module VX_fp_div #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
for (genvar i = 0; i < LANES; i++) begin
wire [LANES-1:0] fdiv_reset;
VX_reset_relay #(
.DEPTH (LANES > 1),
.NUM_NODES (LANES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fdiv_reset)
);
wire fdiv_reset;
VX_reset_relay #(
.NUM_NODES(1)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fdiv_reset)
);
for (genvar i = 0; i < LANES; i++) begin
`ifdef VERILATOR
reg [31:0] r;
fflags_t f;
@@ -59,7 +59,7 @@ module VX_fp_div #(
.RESETW (1)
) shift_req_dpi (
.clk (clk),
.reset (fdiv_reset),
.reset (fdiv_reset[i]),
.enable (enable),
.data_in (r),
.data_out (result[i])
@@ -67,7 +67,7 @@ module VX_fp_div #(
`else
acl_fdiv fdiv (
.clk (clk),
.areset (fdiv_reset),
.areset (fdiv_reset[i]),
.en (enable),
.a (dataa[i]),
.b (datab[i]),

View File

@@ -31,18 +31,18 @@ module VX_fp_sqrt #(
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
wire [LANES-1:0] fsqrt_reset;
VX_reset_relay #(
.DEPTH (LANES > 1),
.NUM_NODES (LANES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fsqrt_reset)
);
for (genvar i = 0; i < LANES; i++) begin
wire fsqrt_reset;
VX_reset_relay #(
.NUM_NODES(1)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fsqrt_reset)
);
for (genvar i = 0; i < LANES; i++) begin
`ifdef VERILATOR
reg [31:0] r;
fflags_t f;
@@ -58,7 +58,7 @@ module VX_fp_sqrt #(
.RESETW (1)
) shift_req_dpi (
.clk (clk),
.reset (fsqrt_reset),
.reset (fsqrt_reset[i]),
.enable (enable),
.data_in (r),
.data_out (result[i])
@@ -66,7 +66,7 @@ module VX_fp_sqrt #(
`else
acl_fsqrt fsqrt (
.clk (clk),
.areset (fsqrt_reset),
.areset (fsqrt_reset[i]),
.en (enable),
.a (dataa[i]),
.q (result[i])