wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

OPAE rtl fixes

Browse Source
This commit is contained in:
Blaise Tine
2020-05-08 13:16:44 -07:00
parent c2e9240b7d
commit 359601cfd3
4 changed files with 11 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
hw/rtl/VX_front_end.v
View File

@@ -50,12 +50,10 @@ module VX_front_end (
.fe_inst_meta_fi (fe_inst_meta_fi) .fe_inst_meta_fi (fe_inst_meta_fi)
); );
wire freeze_fi_reg = total_freeze || icache_stage_delay;
VX_f_d_reg f_i_reg ( VX_f_d_reg f_i_reg (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.freeze (freeze_fi_reg), .freeze (icache_stage_delay),
.fe_inst_meta_fd (fe_inst_meta_fi), .fe_inst_meta_fd (fe_inst_meta_fi),
.fd_inst_meta_de (fe_inst_meta_fi2) .fd_inst_meta_de (fe_inst_meta_fi2)
); );

2
hw/rtl/VX_icache_stage.v
View File

@@ -24,7 +24,7 @@ module VX_icache_stage (
`DEBUG_END `DEBUG_END
// Icache Request // Icache Request
assign icache_req_if.core_req_valid = valid_inst && !total_freeze; assign icache_req_if.core_req_valid = valid_inst;
assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc; assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc;
assign icache_req_if.core_req_data = 'z; assign icache_req_if.core_req_data = 'z;
assign icache_req_if.core_req_read = `BYTE_EN_LW; assign icache_req_if.core_req_read = `BYTE_EN_LW;

8
hw/rtl/cache/VX_cache_dfq_queue.v vendored
View File

@@ -2,13 +2,13 @@
module VX_cache_dfq_queue #( module VX_cache_dfq_queue #(
// Size of cache in bytes // Size of cache in bytes
parameter CACHE_SIZE = 1024, parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes // Size of line inside a bank in bytes
parameter BANK_LINE_SIZE = 16, parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...} // Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8, parameter NUM_BANKS = 8,
// Size of a word in bytes // Size of a word in bytes
parameter WORD_SIZE = 4, parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...} // Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2, parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory) // Number of cycles to complete stage 1 (read from memory)
@@ -35,7 +35,7 @@ module VX_cache_dfq_queue #(
parameter LLVQ_SIZE = 16, parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active} // Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16 parameter FILL_INVALIDAOR_SIZE = 16
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,

7
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
View File

@@ -100,7 +100,9 @@ module VX_cache_dram_req_arb #(
wire dfqq_pop = !dwb_valid && dfqq_req && dram_req_ready; // If no dwb, and dfqq has valids, then pop wire dfqq_pop = !dwb_valid && dfqq_req && dram_req_ready; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (| per_bank_dram_fill_req_valid); wire dfqq_push = (| per_bank_dram_fill_req_valid);
VX_cache_dfq_queue cache_dfq_queue( VX_cache_dfq_queue #(
) cache_dfq_queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.dfqq_push (dfqq_push), .dfqq_push (dfqq_push),
@@ -128,9 +130,10 @@ module VX_cache_dram_req_arb #(
assign per_bank_dram_wb_queue_pop = dram_req_ready ? (use_wb_valid & ((1 << dwb_bank))) : 0; assign per_bank_dram_wb_queue_pop = dram_req_ready ? (use_wb_valid & ((1 << dwb_bank))) : 0;
wire dram_req_valid = dwb_valid || dfqq_req || pref_pop; wire dram_req_valid = dwb_valid || dfqq_req || pref_pop;
assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req_valid; assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req_valid;
assign dram_req_write = dwb_valid && dram_req_valid; assign dram_req_write = dwb_valid && dram_req_valid;
assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr); assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr);
assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0; assign {dram_req_data} = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;
endmodule endmodule