wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

multiplier unit optimization - using fifo for metadata, shift register optimization

Browse Source
This commit is contained in:
Blaise Tine
2020-12-26 11:23:21 -08:00
parent b459192dec
commit 33c431ed44
13 changed files with 171 additions and 76 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hw/rtl/libs/VX_divide.v → hw/rtl/libs/VX_divider.v
View File

@@ -1,6 +1,6 @@
`include "VX_platform.vh"
module VX_divide #(
module VX_divider #(
parameter WIDTHN = 1,
parameter WIDTHD = 1,
parameter WIDTHQ = 1,

101
hw/rtl/libs/VX_shift_register.v
View File

@@ -1,14 +1,105 @@
`include "VX_platform.vh"
module VX_shift_register #(
parameter DATAW = 1,
parameter RESETW = DATAW,
parameter DEPTH = 1
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
);
if (RESETW != 0) begin
if (RESETW == DATAW) begin
VX_shift_register_wr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in),
.data_out (data_out)
);
end else begin
VX_shift_register_wr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr_wr (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in[DATAW-1:DATAW-RESETW]),
.data_out (data_out[DATAW-1:DATAW-RESETW])
);
VX_shift_register_nr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr_nr (
.clk (clk),
.enable (enable),
.data_in (data_in[DATAW-RESETW-1:0]),
.data_out (data_out[DATAW-RESETW-1:0])
);
end
end else begin
`UNUSED_VAR (reset)
VX_shift_register_nr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr (
.clk (clk),
.enable (enable),
.data_in (data_in),
.data_out (data_out)
);
end
endmodule
module VX_shift_register_nr #(
parameter DATAW = 1,
parameter DEPTH = 1
) (
input wire clk,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
);
reg [DATAW-1:0] entries [DEPTH-1:0];
always @(posedge clk) begin
if (enable) begin
for (integer i = DEPTH-1; i > 0; --i)
entries[i] <= entries[i-1];
entries[0] <= data_in;
end
end
assign data_out = entries [DEPTH-1];
endmodule
module VX_shift_register_wr #(
parameter DATAW = 1,
parameter DEPTH = 1
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] in,
output wire [DATAW-1:0] out
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
);
reg [DEPTH-1:0][DATAW-1:0] entries;
@@ -19,7 +110,7 @@ module VX_shift_register #(
entries <= (DEPTH * DATAW)'(0);
end else begin
if (enable) begin
entries <= in;
entries <= data_in;
end
end
end
@@ -31,12 +122,12 @@ module VX_shift_register #(
entries <= (DEPTH * DATAW)'(0);
end else begin
if (enable) begin
entries <= {entries[DEPTH-2:0], in};
entries <= {entries[DEPTH-2:0], data_in};
end
end
end
end
assign out = entries [DEPTH-1];
assign data_out = entries [DEPTH-1];
endmodule