adding fpu_core synthesis build

hw/syn/quartus/.gitignore

@@ -7,6 +7,9 @@
 /cache/*
 !/cache/Makefile
 
+/fpu_core/*
+!/fpu_core/Makefile
+
 /vortex/*
 !/vortex/Makefile
 

hw/syn/quartus/Makefile

@@ -1,6 +1,6 @@
 BUILD_DIR ?= build
 
-.PHONY: unittest pipeline smem cache core vortex top1 top2 top4 top8 top16 top32 top64
+.PHONY: unittest pipeline smem cache fpu_core core vortex top1 top2 top4 top8 top16 top32 top64
 
 unittest:
 	mkdir -p unittest/$(BUILD_DIR)
@@ -22,6 +22,11 @@ cache:
 	cp cache/Makefile cache/$(BUILD_DIR)
 	$(MAKE) -C cache/$(BUILD_DIR) clean && $(MAKE) -C cache/$(BUILD_DIR) > cache/$(BUILD_DIR)/build.log 2>&1 &
 
+fpu_core:
+	mkdir -p fpu_core/$(BUILD_DIR)
+	cp fpu_core/Makefile fpu_core/$(BUILD_DIR)
+	$(MAKE) -C fpu_core/$(BUILD_DIR) clean && $(MAKE) -C fpu_core/$(BUILD_DIR) > fpu_core/$(BUILD_DIR)/build.log 2>&1 &
+
 core:
 	mkdir -p core/$(BUILD_DIR)
 	cp core/Makefile core/$(BUILD_DIR)

hw/syn/quartus/fpu_core/Makefile

@@ -0,0 +1,86 @@
+PROJECT = VX_fpu_fpga
+TOP_LEVEL_ENTITY = VX_fpu_fpga
+SRC_FILE = VX_fpu_fpga.v
+RTL_DIR = ../../../../rtl
+
+FAMILY = "Arria 10"
+DEVICE = 10AX115N3F40E2SG
+FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
+
+#FAMILY = "Stratix 10"
+#DEVICE = 1SX280HN2F43E2VG
+#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
+
+FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
+RTL_INCLUDE = $(FPU_INCLUDE);$(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces
+PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
+
+# Part, Family
+FAMILY = "Arria 10"
+DEVICE = 10AX115N3F40E2SG   
+
+# Executable Configuration
+SYN_ARGS = --parallel --read_settings_files=on
+FIT_ARGS = --parallel --part=$(DEVICE) --read_settings_files=on
+ASM_ARGS =
+STA_ARGS = --parallel --do_report_timing
+
+# Build targets
+all: $(PROJECT).sta.rpt
+
+syn: $(PROJECT).syn.rpt
+
+fit: $(PROJECT).fit.rpt
+
+asm: $(PROJECT).asm.rpt
+
+sta: $(PROJECT).sta.rpt
+
+smart: smart.log
+
+# Target implementations
+STAMP = echo done >
+
+$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) 
+	quartus_syn $(PROJECT) $(SYN_ARGS)
+	$(STAMP) fit.chg
+
+$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
+	quartus_fit $(PROJECT) $(FIT_ARGS)
+	$(STAMP) asm.chg
+	$(STAMP) sta.chg
+
+$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
+	quartus_asm $(PROJECT) $(ASM_ARGS)
+
+$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
+	quartus_sta $(PROJECT)  $(STA_ARGS) 
+
+smart.log: $(PROJECT_FILES)
+	quartus_sh --determine_smart_action $(PROJECT) > smart.log
+
+# Project initialization
+$(PROJECT_FILES):
+	quartus_sh -t ../../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src "$(SRC_FILE)" -sdc ../../project.sdc -inc "$(RTL_INCLUDE)"
+# -set "FPU_CVT2"
+	
+syn.chg:
+	$(STAMP) syn.chg
+
+fit.chg:
+	$(STAMP) fit.chg
+
+sta.chg:
+	$(STAMP) sta.chg
+
+asm.chg:
+	$(STAMP) asm.chg
+
+timing: $(PROJECT_FILES)
+	quartus_sh -t ../../timing-html.tcl -project $(PROJECT)
+
+program: $(PROJECT).sof
+	quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
+
+clean:
+	rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws *.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox