rtl gpr multicore fix

2020-05-06 09:05:10 -04:00
parent b1fdf0a947
commit 330bbc4f56
18 changed files with 210 additions and 200 deletions
--- a/hw/rtl/cache/VX_cache_dram_req_arb.v
+++ b/hw/rtl/cache/VX_cache_dram_req_arb.v
@@ -113,7 +113,7 @@ module VX_cache_dram_req_arb #(
        .dfqq_full                      (dfqq_full)
    );

-    wire [`LOG2UP(NUM_BANKS)-1:0] dwb_bank;
+    wire [`BANK_BITS-1:0] dwb_bank;

    wire [NUM_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req_valid;